View KSZ8895ML_8415363.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KSZ8895MLub integrated 5 - port 10/100 managed switch revision 2. 1 general description the KSZ8895MLub is a highly - integrated layer 2 - managed 5- port switch with an optimized design and plentiful features, qualified to meet aec - q100 standard for automotive applications. it is designed for cost - sensitive 10/100mbps 5 - port switch systems with on - chip termination, lowest power consumption and internal core power controller. these features will save more system cost . it has 1.4gbps high - performance memory bandwidth, shared memory based switch fabric with full non - blocking con figuration. it also provides an extensive feature set such as power management, programmable rate limit and priority ratio , tag/port - based vlan, packets filtering, quality - of - service (qos) four - queue priorit ization , management interface , and mib counters . p ort 5 is a mac 5 mii interface with phy mode as default at switch side . the sw5 - mii interface can be connected to a processor with a mac mii interface. the KSZ8895MLub consists of 10/100 phys with patented and enhanced mixed - signal technology , m edia acc ess control (mac) units, a high - speed non - blocking switch fabric, a dedicated address lookup engine, and an on - chip frame buffer memory. the KSZ8895MLub contains five macs and four integrated phys. all phys support 10/100base - t/tx. all registers of macs a nd phy s units can be managed by the spi interface or the smi interface . miim registers of the phys can be accessed through the mdc/mdio interface . eeprom can set all control registers for the unmanaged mode. the KSZ8895MLub provides multiple cpu control/da ta interfaces to effectively address both current and emerging fast ethernet applications. datasheets and support documentation are available on micrels web site at: www.micrel.com . functional diagram micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com april 1, 2 014 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub features advanced switch features ? ieee 802.1q vlan support for up to 128 vlan groups (full- range 4096 of vlan ids) . ? static mac table supports up to 32 entries. ? vlan id tag/untag options, per port basis . ? ieee 802.1p/q tag insertion or removal on a per port basis based on ingress port (egress) . ? programmable rate limiting at the ingress and egress on a per port basis . ? ji tter - free per packet based rate - limiting support . ? broadcast storm protection with percentage control (global and per port basis) . ? ieee 802.1d rapid s panning tree protocol rstp support . ? tail tag mode (1byte added before fcs) support at port 5 to inform the processor which ingress port receives the packet . ? 1.4 gbps high - performance memory bandwidth and s hared memory - based switch fabric with fully non - bloc king configuration . ? mii with mac 5 on port 5, sw 5- mii for mac 5 mii interface . ? e nable/disable option for huge frame size up to 2000 b ytes per frame . ? igmp v1/v2 snooping (ipv4 ) support for multicast packet f iltering . ? ipv4/ipv6 qo s support . ? support unknown u nicast/multicast address and unknown vid packet filtering . ? s elf - address filtering . comprehensive configuration register access ? serial management interface (mdc/mdio) to all phy s registers and smi interface (mdc/mdio) to all registers. ? high - speed spi (up to 25mhz) and i 2 c master interface to all internal registers. ? i/0 pins strapping and eeprom to program selective registers in unmanaged switch mode. ? control registers configurable on the fly (port -priority, 802.1p/d/q, an). qos/cos packet prioritization sup port ? p er port, 802.1p and diffserv - based. ? 1/2/4 - queue qos prioritization selection. ? programmable weighted fair queuing for ratio control. ? re- mapping of 802.1p priority field per port basis. integrated 5 - port 10/100 ethernet switch ? new generation switch with five macs and five phys fully compliant with ieee 802.3u standard. ? non - blocking switch fabric assures fast packet delivery by utilizing a 1k mac address lookup table and a store - and - forward architecture. ? on - chip 64kbyte memory for frame buffering (not shared with 1k unicast address table). ? full duplex ieee 802.3x flow control (pause) with force mode option . ? half - duplex back pressure flow control . ? hp auto mdi/mdi - x and ieee auto crossover support . ? port 5 mac5 sw 5- mii interface supports phy mode and mac mo de . ? 7- wire serial network interface (sni) support for legacy mac . ? per port led indicators for link, activity, and 10/100 speed . ? r egister port status support for link, activity, full/half duplex and 10/100 speed . ? micrel linkmd? cable diagnostic capabilities for determining cable opens, shorts, and length . ? on- chip terminations and internal biasing technology for cost down and lowest power consumption. switch monitoring features ? port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or m ii. ? m ib counters for fully - compliant statistics gathering 34 mib counters per port. ? loop - back support for mac, phy, and remote diagnostic of failure. ? interrupt for the link change on any ports. low power dissipation ? full - chip hardware power - down . ? full - chip software power - down /per port software power down . ? energy - detect mode support < 100m w full - chip power consumption when all ports have no activity . ? very- low , full - chip power consumption (<0.5w) , without extra power consumption on transformers . ? dynamic clock - tree shutdown feature . ? v oltages: single 3.3v supply with 3.3v vddio and internal 1.2v ldo controller enabled or external 1.2v ldo solution : ? analog vddat 3.3v only ? vddio support 3.3v, 2.5v and 1.8v ? low 1.2v core power ? i ndustrial temperature range: C 40 o c to +85 o c. ? available in 128 -p in l qfp, l ead - free package . applications ? in - vehicle diagnostics (obd) ? high - speed software download ? gateway switch ? head unit ? rear seat entertainment april 1, 2014 2 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub ordering information part number temperature range package lead finish/ grade KSZ8895MLub (automotive grade) ? 40 c to +85 c 128 - pin lqfp pb- free/ automotive KSZ8895MLub - eval board evaluation board for KSZ8895MLub revision history revision date summary of changes 1.0 03/16/11 initial 1.1 09/2 7/11 u pdate some descriptions , updates for descriptions of smi mode and igmp mode, update register default values, pins type and some parameters. revision 1.1 datasheet reflects the revision a4 silicon ( 0. 13um cmos technology ). 2.0 0 2/21 /14 updates timing data for mii phy mode. updat e descriptions for vlan table and i2c master mode . update the descriptions for the pins 125 and 126. update the equation in the broadcast storm protection section . update the operation rating to +/ - 5% and ttl min/max i/o voltage in different vddio. chan ge i/o from ttl to cmos. update spi description from 127 to 255 for all registers. update the table of tail tag rules. update description for register 1 bits [7:4]. update table 8 from bit [57:55] to bit [58:56]. update the port register control 2 bit [6] description bits [20:16] change to bits [11:7]. add evaluation board in the ordering information table. revision 2.0 datasheet reflects the revision b2 silicon ( 0. 11 um cmos technology ). from b2 s ilicon, add linkmd feature and esd to be improved to 5 kv. 2.1 0 3/31 /14 the part number is changed from ksz8895 mlu to KSZ8895MLub . remove port 5 in the pin configuration and pin description. update notes description for pin 125 and pin 126 in the pins descriptions. update operating rating and electrical char acteristics, correct typos. april 1, 2014 3 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub contents list of figures ...................................................................................................................................................................... 13 list of tables ....................................................................................................................................................................... 14 pin configuration ................................................................................................................................................................ 15 pin description .................................................................................................................................................................... 16 pin for strap - in options ...................................................................................................................................................... 22 introduction ......................................................................................................................................................................... 25 physical layer transceiver ................................................................................................................................................ 25 100base - tx transmit ..................................................................................................................................................... 25 10base - t transmit .......................................................................................................................................................... 25 10base - t receive ........................................................................................................................................................... 26 mdi/mdi - x auto crossover .............................................................................................................................................. 26 auto - negotiation ............................................................................................................................................................... 27 linkmd ? cable diagnostics .............................................................................................................................................. 29 on - chip termination resist ors ........................................................................................................................................ 30 internal 1.2v ldo controller ............................................................................................................................................ 30 power management ............................................................................................................................................................ 31 norma l operation mode ................................................................................................................................................... 31 energy detect mode ......................................................................................................................................................... 31 soft power - down mode .................................................................................................................................................... 32 power - saving mode .......................................................................................................................................................... 32 port - based power - down mode ........................................................................................................................................ 32 switch core ....................................................................................................................................................................... 32 address look - up .............................................................................................................................................................. 32 learning ............................................................................................................................................................................ 32 migration ........................................................................................................................................................................... 32 aging ................................................................................................................................................................................. 32 forwarding ........................................................................................................................................................................ 33 switching engine .............................................................................................................................................................. 33 media access controller (mac) operati on ...................................................................................................................... 33 mii interface operation ..................................................................................................................................................... 36 port 5 mac 5 sw5 - mii interface ...................................................................................................................................... 36 sni interface operation .................................................................................................................................................... 37 april 1, 2014 4 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced functionality ...................................................................................................................................................... 39 qos priority support ......................................................................................................................................................... 39 port - based priority ............................................................................................................................................................ 39 802.1p - based priority ....................................................................................................................................................... 39 spanning tree support ..................................................................................................................................................... 40 rapid spanning tree support .......................................................................................................................................... 41 tail tagging mode ............................................................................................................................................................ 41 igmp support ................................................................................................................................................................... 42 port mirroring support ...................................................................................................................................................... 43 vlan support ................................................................................................................................................................... 43 rate limiting support ....................................................................................................................................................... 44 ingress rate limit ............................................................................................................................................................. 44 egress rate limit .............................................................................................................................................................. 44 transmit queue ratio programming ................................................................................................................................ 45 filtering for self - address, unknown unicast/multicast address and unknown vid packet/ip multicast ........................ 45 configuration interfaces ..................................................................................................................................................... 46 i 2 c master serial bus configuration ................................................................................................................................ . 46 spi slave serial bus configuration .................................................................................................................................. 46 mi i management interface (miim) .................................................................................................................................... 49 serial management interface (smi) .................................................................................................................................. 49 register description ........................................................................................................................................................... 51 global registers .................................................................................................................................................................. 53 register 0 (0 00): chip id0 .............................................................................................................................................. 53 register 1 (0 01): chip id1 / start switch ........................................................................................................................ 53 register 2 (0 02): global control 0 .................................................................................................................................. 53 register 2 (0 02): global control 0 .................................................................................................................................. 54 register 3 (0 03): global control 1 .................................................................................................................................. 54 register 3 (0 03): global control 1 .................................................................................................................................. 55 register 4 (0 04): global control 2 .................................................................................................................................. 56 register 4 (0 04): global control 2 .................................................................................................................................. 57 register 5 (0 05): global control 3 .................................................................................................................................. 57 register 6 (0 06 ): global control 4 .................................................................................................................................. 58 register 7 (0 07): global control 5 .................................................................................................................................. 59 register 8 (0 08): global control 6 .................................................................................................................................. 59 register 9 (0 09): global control 7 .................................................................................................................................. 59 register 10 (0 0a): global control 8 ................................................................................................................................ 59 april 1, 2014 5 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub register 11 (0 0b): global control 9 ................................................................................................................................ 59 register 11 (0 0b): global control 9 ................................................................................................................................ 60 register 12 (0 0c): global c ontrol 10 ............................................................................................................................. 61 register 13 (0 0d): global control 11 ............................................................................................................................. 61 register 14 (0 0e): power - down management control 1 ............................................................................................... 62 register 14 (0 0e): power - down management control 1 ............................................................................................... 62 register 15 (0 0f): power - down management control 2 ............................................................................................... 62 port registers ...................................................................................................................................................................... 63 register 16 (0 10): port 1 control 0 ................................................................................................................................ . 63 register 32 (0 20): port 2 control 0 ................................................................................................................................ . 63 register 48 (0 30): port 3 control 0 ................................................................................................................................ . 63 register 64 (0 40): port 4 control 0 ................................................................................................................................ . 63 register 80 (0 50): port 5 control 0 ................................................................................................................................ . 63 register 16 (0 10): port 1 control 0 ................................................................................................................................ . 64 register 32 (0 20): port 2 control 0 ................................................................................................................................ . 64 register 48 (0 30): port 3 control 0 ................................................................................................................................ . 64 register 64 (0 40): port 4 control 0 ................................................................................................................................ . 64 register 80 (0 50): port 5 control 0 ................................................................................................................................ . 64 register 17 (0 11): port 1 control 1 ................................................................................................................................ . 64 register 33 (0 21): port 2 control 1 ................................................................................................................................ . 64 register 49 (0 31): port 3 control 1 ................................................................................................................................ . 64 register 65 (0 41): port 4 control 1 ................................................................................................................................ . 64 register 81 (0 51): port 4 control 1 ................................................................................................................................ . 64 register 18 (0 12): port 1 control 2 ................................................................................................................................ . 65 register 34 (0 22): port 2 control 2 ................................................................................................................................ . 65 register 50 (0 32): port 3 control 2 ................................................................................................................................ . 65 register 66 (0 42): port 4 control 2 ................................................................................................................................ . 65 register 82 (0 52): port 5 control 2 ................................................................................................................................ . 65 register 18 (0 12): port 1 control 2 ................................................................................................................................ . 66 register 34 (0 22): port 2 control 2 ................................................................................................................................ . 66 register 50 (0 32): port 3 control 2 ................................................................................................................................ . 66 register 66 (0 42): port 4 control 2 ................................................................................................................................ . 66 register 82 (0 52): port 5 control 2 ................................................................................................................................ . 66 register 19 (0 13): port 1 control 3 ................................................................................................................................ . 67 reg ister 35 (0 23): port 2 control 3 ................................................................................................................................ . 67 register 51 (0 33): port 3 control 3 ................................................................................................................................ . 67 april 1, 2014 6 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub register 67 (0 43): port 4 control 3 ................................................................................................................................ . 67 register 83 (0 53): port 5 control 3 ................................................................................................................................ . 67 register 20 (0 14): port 1 control 4 ................................................................................................................................ . 67 register 36 (0 24): port 2 control 4 ................................................................................................................................ . 67 register 52 (0 34): port 3 control 4 ................................................................................................................................ . 67 register 68 (0 44): port 4 control 4 ................................................................................................................................ . 67 register 84 (0 54): port 5 control 4 ................................................................................................................................ . 67 register 87 (0 57): reserved control register ............................................................................................................... 67 register 25 (0 19): port 1 status 0 .................................................................................................................................. 68 register 41 (0 29): port 2 status 0 .................................................................................................................................. 68 register 57 (0 39): port 3 status 0 .................................................................................................................................. 68 register 73 (0 49): port 4 status 0 .................................................................................................................................. 68 register 89 (0 59): reserved ........................................................................................................................................... 68 register 26 (0 1a): port 1 phy special control/status ................................................................................................... 68 register 42 (0 2a): port 2 phy special control/status ................................................................................................... 68 register 58 (0 3a): port 3 phy special control/status ................................................................................................... 68 register 74 (0 4a): port 4 phy special control/status ................................................................................................... 68 register 90 (0 5a): reserved .......................................................................................................................................... 68 register 27 (0 1b): port 1 linkmd result ....................................................................................................................... 69 register 43 (0 2b): port 2 linkmd result ....................................................................................................................... 69 register 59 (0 3b): port 3 linkmd result ....................................................................................................................... 69 register 75 (0 4b): port 4 linkmd result ....................................................................................................................... 69 register 91 (0 5b): reserved .......................................................................................................................................... 69 register 28 (0 1c): port 1 control 5 ................................................................................................................................ 69 register 44 (0 2c): port 2 control 5 ................................................................................................................................ 69 register 60 (0 3c): port 3 control 5 ................................................................................................................................ 69 register 76 (0 4c): port 4 control 5 ................................................................................................................................ 69 register 92 (0 5c): reserved .......................................................................................................................................... 69 register 28 (0 1c): port 1 control 5 ................................................................................................................................ 70 register 44 (0 2c): port 2 control 5 ................................................................................................................................ 70 register 60 (0 3c): port 3 control 5 ................................................................................................................................ 70 register 76 (0 4c): port 4 control 5 ................................................................................................................................ 70 register 92 (0 5c): reserved .......................................................................................................................................... 70 register 29 (0 1d): port 1 control 6 ................................................................................................................................ 70 register 45 (0 2d): port 2 control 6 ................................................................................................................................ 70 register 61 (0 3d): port 3 control 6 ................................................................................................................................ 70 april 1, 2014 7 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub register 77 (0 4d): port 4 control 6 ................................................................................................................................ 70 register 93 (0 5d): reserved .......................................................................................................................................... 70 register 29 (0 1d): port 1 control 6 ................................................................................................................................ 71 register 45 (0 2d): port 2 control 6 ................................................................................................................................ 71 register 61 (0 3d): port 3 control 6 ................................................................................................................................ 71 register 77 (0 4d): port 4 control 6 ................................................................................................................................ 71 register 93 (0 5d): reserved .......................................................................................................................................... 71 register 30 (0 1e): port 1 status 1 .................................................................................................................................. 71 register 46 (0 2e): port 2 status 1 .................................................................................................................................. 71 register 62 (0 3e): port 3 status 1 .................................................................................................................................. 71 register 78 (0 4e): port 4 status 1 .................................................................................................................................. 71 register 94 (0 5e): reserved .......................................................................................................................................... 71 register 31 (0 1f): port 1 control 7 and status 2 ........................................................................................................... 72 register 47 (0 2f): port 2 control 7 and status 2 ........................................................................................................... 72 register 63 (0 3f): port 3 control 7 and status 2 ........................................................................................................... 72 register 79 (0 4f): port 4 control 7 and status 2 ........................................................................................................... 72 register 95 (0 5f): reserved .......................................................................................................................................... 72 advanced control registers .............................................................................................................................................. 73 register 104 (0 68): mac address register 0 ................................................................................................................ 73 register 105 (0 69): mac address register 1 ................................................................................................................ 73 register 106 (0 6a): mac address register 2 ................................................................................................................ 73 register 107 (0 6b): mac address register 3 ................................................................................................................ 73 register 108 (0 6c): mac address register 4 ................................................................................................................ 73 register 109 (0 6d): mac address register 5 ................................................................................................................ 73 register 110 (0 6e): indirect access control 0 ............................................................................................................... 74 register 111 (0 6f): indirect access control 1 ................................................................................................................ 74 register 112 (0 70): indirect data register 8 .................................................................................................................. 74 register 113 (0 71): indirect data register 7 .................................................................................................................. 74 register 114 (0 72): indirect data register 6 .................................................................................................................. 74 register 115 (0 73): indirect data register 5 .................................................................................................................. 74 register 116 (0 74): indirect data register 4 .................................................................................................................. 74 register 117 (0 75): indirect data register 3 .................................................................................................................. 75 register 118 (0 76): indirect data register 2 .................................................................................................................. 75 register 119 (0 77): indirect data register 1 .................................................................................................................. 75 regist er 120 (0 78): indirect data register 0 .................................................................................................................. 75 register 124 (0x7c): interrupt status register ................................................................................................................ 75 april 1, 2014 8 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub register 125 (0x7d): interrupt mask register .................................................................................................................. 76 register 128 (0x80): global control 12 ............................................................................................................................ 76 register 129 (0x81): global control 13 ............................................................................................................................ 76 register 130 (0x82): global control 14 ............................................................................................................................ 77 register 131 (0x83): global control 15 ............................................................................................................................ 77 register 132 (0x84): global control 16 ............................................................................................................................ 78 register 133(0x85): global control 17 ............................................................................................................................. 78 register 134 (0x86): global control 18 ............................................................................................................................ 79 register 135 (0x87): global control 19 ............................................................................................................................ 79 register 144 (0x90): tos priority control register 0 ...................................................................................................... 80 register 145 (0x91): tos priority control register 1 ...................................................................................................... 80 register 146 (0x92): tos priority control register 2 ...................................................................................................... 80 register 147 (0x93): tos priority control register 3 ...................................................................................................... 80 register 148 (0x94): tos priority control register 4 ...................................................................................................... 81 register 149 (0x95): tos priority control register 5 ...................................................................................................... 81 register 150 (0x96): tos priority control register 6 ...................................................................................................... 81 register 151 (0x97): tos priority control register 7 ...................................................................................................... 81 register 152 (0x98): tos priority control register 8 ...................................................................................................... 81 register 153 (0x99): tos priority control re gister 9 ...................................................................................................... 82 register 154 (0x9a): tos priority control register 10 .................................................................................................... 82 register 155 (0x9b): tos priority control register 11 .................................................................................................... 82 register 156 (0x9c): tos priority control register 12 .................................................................................................... 82 register 157 (0x9d): tos priority control register 13 .................................................................................................... 82 register 158 (0x9e): tos priority control register 14 .................................................................................................... 83 register 159 (0x9f): tos priority control register 15 .................................................................................................... 83 register 176 (0xb0): port 1 control 8 ............................................................................................................................... 83 register 192 (0xc0): port 2 control 8 .............................................................................................................................. 83 register 208 (0xd0): port 3 control 8 .............................................................................................................................. 83 register 224 (0xe0): port 4 control 8 ............................................................................................................................... 83 register 240 (0xf0): port 5 control 8 ............................................................................................................................... 83 register 176 (0xb0): port 1 control 8 ............................................................................................................................... 84 register 192 (0xc0): port 2 control 8 .............................................................................................................................. 84 register 208 (0xd0): port 3 control 8 .............................................................................................................................. 84 register 224 (0xe0): port 4 control 8 ............................................................................................................................... 84 register 240 (0xf0): port 5 control 8 ............................................................................................................................... 84 register 177 (0xb1): port 1 control 9 ............................................................................................................................... 84 register 193 (0xc1): port 2 control 9 .............................................................................................................................. 84 april 1, 2014 9 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub register 209 (0xd1): port 3 control 9 .............................................................................................................................. 84 register 225 (0xe1): port 4 control 9 ............................................................................................................................... 84 register 241 (0xf1): port 5 cont rol 9 ............................................................................................................................... 84 register 178 (0xb2): port 1 control 10 ............................................................................................................................ 85 register 194 (0xc2): port 2 control 10 ............................................................................................................................ 85 register 210 (0xd2): port 3 control 10 ............................................................................................................................ 85 register 226 (0xe2): port 4 control 10 ............................................................................................................................ 85 register 242 (0xf2): port 5 control 10 ............................................................................................................................. 85 register 179 (0xb3): port 1 control 11 ............................................................................................................................ 85 register 195 (0xc3): port 2 control 11 ............................................................................................................................ 85 register 211 (0xd3): port 3 control 11 ............................................................................................................................ 85 register 227 (0xe3): port 4 control 11 ............................................................................................................................ 85 register 243 (0xf3): port 5 control 11 ............................................................................................................................. 85 register 180 (0xb4): port 1 control 12 ............................................................................................................................ 85 register 196 (0xc4): port 2 control 12 ............................................................................................................................ 85 register 212 (0xd4): port 3 control 12 ............................................................................................................................ 85 register 228 (0xe4): port 4 control 12 ............................................................................................................................ 85 register 244 (0xf4): port 5 control 12 ............................................................................................................................. 85 register 181 (0xb5): port 1 control 13 ............................................................................................................................ 86 register 197 (0xc5): po rt 2 control 13 ............................................................................................................................ 86 register 213 (0xd5): port 3 control 13 ............................................................................................................................ 86 register 229 (0xe5): port 4 control 13 ............................................................................................................................ 86 register 245 (0xf5): port 5 control 13 ............................................................................................................................. 86 register 182 (0xb6): port 1 rate limit control ................................................................................................................ 86 register 198 (0xc6): port 2 rate limit control ................................................................................................................ 86 register 214 (0xd6): port 3 rate limit control ................................................................................................................ 86 register 230 (0xe6): port 4 rate limit control ................................................................................................................ 86 register 246 (0xf6): port 5 rate limit control ................................................................................................................ 86 register 183 (0xb7): port 1 priority 0 ingress limit control 1 .......................................................................................... 87 register 199 (0xc7): port 2 priority 0 ingress limit control 1 .......................................................................................... 87 register 215 (0xd7): port 3 priority 0 ingress li mit control 1 .......................................................................................... 87 register 231 (0xe7): port 4 priority 0 ingress limit control 1 .......................................................................................... 87 register 247 (0xf7): port 5 priority 0 ingres s limit control 1 .......................................................................................... 87 register 184 (0xb8): port 1 priority 1 ingress limit control 2 .......................................................................................... 87 register 200 (0xc8): port 2 priority 1 ingress limit control 2 .......................................................................................... 87 register 216 (0xd8): port 3 priority 1 ingress limit control 2 .......................................................................................... 87 register 232 (0xe8): port 4 priority 1 ingress limit control 2 .......................................................................................... 87 april 1, 2014 10 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub register 248 (0xf8): port 5 priority 1 ingress limit control 2 .......................................................................................... 87 register 185 (0xb9): port 1 priority 2 ingress limit control 3 .......................................................................................... 87 register 201 (0xc9): port 2 priority 2 ingress limit control 3 .......................................................................................... 87 register 217 (0xd9): port 3 p riority 2 ingress limit control 3 .......................................................................................... 87 register 233 (0xe9): port 4 priority 2 ingress limit control 3 .......................................................................................... 87 register 249 (0xf9): port 5 priority 2 ingress limit control 3 .......................................................................................... 87 register 186 (0xba): port 1 priority 3 ingress limit control 4 ......................................................................................... 88 register 202 (0xca): port 2 priority 3 ingress limit control 4 ......................................................................................... 88 register 218 (0xda): port 3 priority 3 ingress limit control 4 ......................................................................................... 88 register 234 (0xe a): port 4 priority 3 ingress limit control 4 ......................................................................................... 88 register 250 (0xfa): port 5 priority 3 ingress limit control 4 .......................................................................................... 88 register 187 (0xbb): port 1 queue 0 egress limit control 1 .......................................................................................... 88 register 203 (0xcb): port 2 queue 0 egress limit control 1 .......................................................................................... 88 register 219 (0xdb): port 3 queue 0 egress limit control 1 .......................................................................................... 88 register 235 (0xeb): port 4 queue 0 egress limit control 1 .......................................................................................... 88 register 251 (0xfb): port 5 queue 0 egress limit control 1 ........................................................................................... 88 register 188 (0xbc): port 1 queue 1 egress limit control 2 .......................................................................................... 88 register 204 (0xcc): port 2 queue 1 egress limit control 2 .......................................................................................... 88 register 220 (0xdc): port 3 queue 1 egress limit control 2 .......................................................................................... 88 register 236 (0xec): port 4 queue 1 egress limit control 2 .......................................................................................... 88 register 252 (0xfc): port 5 queue 1 egress limit control 2 .......................................................................................... 88 register 189 (0xbd): port 1 queue 2 egress limit control 3 .......................................................................................... 89 register 205 (0xcd): port 2 queue 2 egress limit control 3 .......................................................................................... 89 register 221 (0xdd): port 3 queue 2 egress limit control 3 .......................................................................................... 89 register 237 (0xed): port 4 queue 2 egress limit control 3 .......................................................................................... 89 register 253 (0xfd): port 5 queue 2 egres s limit control 3 .......................................................................................... 89 register 190 (0xbe): port 1 queue 3 egress limit control 4 .......................................................................................... 89 register 206 (0xce): port 2 queue 3 egress limit control 4 .......................................................................................... 89 register 222 (0xde): port 3 queue 3 egress limit control 4 .......................................................................................... 89 register 238 (0xee): port 4 queue 3 egress limit control 4 .......................................................................................... 89 register 254 (0xfe): port 5 queue 3 egress limit control 4 ........................................................................................... 89 register 191(0xbf): testing register .............................................................................................................................. 91 register 207(0xcf): reserved control register ............................................................................................................. 91 register 223(0xdf): test register 2 ................................................................................................................................ 91 register 239(0xef): test register 3 ................................................................................................................................ 91 register 255(0xff): testing register 4 ............................................................................................................................. 91 april 1, 2014 11 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub static mac address table ................................................................................................................................................. 92 vlan table .......................................................................................................................................................................... 94 dynamic mac address table ............................................................................................................................................ 96 management information base (mib) counters ............................................................................................................... 98 port 1 mib counter indirect memory offsets .................................................................................................................... 98 format of per port mib counter ..................................................................................................................................... 99 miim registers ................................................................................................................................................................... 102 register 0h: mii control .................................................................................................................................................. 102 register 1h: mii status ................................................................................................................................................... 103 register 2h: phyid high .............................................................................................................................................. 103 register 3h: phyid low ............................................................................................................................................... 103 register 4h: advertisemen t ability .................................................................................................................................. 104 register 5h: link partner ability ..................................................................................................................................... 104 register 1dh: linkmd control/status ............................................................................................................................ 105 register 1fh: phy special control/status ...................................................................................................................... 105 absolute maximum ratings ............................................................................................................................................. 107 operating ratings ............................................................................................................................................................. 107 electrical characteristics ................................................................................................................................................. 107 timing diagrams ............................................................................................................................................................... 109 eeprom timing ............................................................................................................................................................. 109 sni timing ...................................................................................................................................................................... 110 spi timing ...................................................................................................................................................................... 113 auto - negotiation timing ................................................................................................................................................. 115 reset timing ................................................................................................................................................................... 116 reset circuit diagram ..................................................................................................................................................... 117 isolation transformer sel ection ...................................................................................................................................... 11 8 reference crystal selection ............................................................................................................................................. 118 package information ......................................................................................................................................................... 119 april 1, 2014 12 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub list of figures figure 1. typical straight cable connection ........................................................................................................................ 26 figure 2. typical crossover cable connection .................................................................................................................... 27 figure 3. auto - negotiation .................................................................................................................................................... 28 figure 4. destination address lookup flow chart (stage 1) ............................................................................................... 34 figure 5. destination address resolution flow chart (stage 2) .......................................................................................... 35 figure 6. 802.1p priority field format .................................................................................................................................. 39 figure 7. tail tag frame format .......................................................................................................................................... 41 figure 8. KSZ8895MLub eeprom c onfiguration timing diagram .................................................................................... 46 figure 9. spi write data cycle ............................................................................................................................................. 47 figure 10. spi read data cycle ........................................................................................................................................... 47 figure 11. spi multiple write ................................................................................................................................................ 48 figure 12. spi multiple read ................................................................................................................................................ 48 figure 13. eeprom interface input receive timing diagram ........................................................................................... 109 figure 14. eeprom interface output transmit timing diagram ....................................................................................... 109 figure 15. sni input timing ................................................................................................................................................ 110 figure 16. sni output timing ............................................................................................................................................. 110 figure 17. mac mode mii timing C data received from mii ............................................................................................. 111 figure 18. mac mode mii timing C data transmitted from mii ......................................................................................... 111 figure 19. phy mode mii timing C data received from mii .............................................................................................. 112 figure 20. phy mode mii timing C data transmitted from mii .......................................................................................... 112 figure 21. spi input timing ................................................................................................................................................ 113 figure 22. spi output timing .............................................................................................................................................. 114 figure 23. auto - negotiation timing .................................................................................................................................... 115 figure 24. reset timing ...................................................................................................................................................... 116 figure 25. recommended reset circuit ............................................................................................................................. 117 figure 26. recommended circuit for interfacing with cpu/fpga reset ........................................................................... 117 april 1, 2014 13 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub list of tables table 1. mdi/mdi - x pin definitions ...................................................................................................................................... 26 table 2. internal function block status ................................................................................................................................ 31 table 3. switch mac 5 mii signals ....................................................................................................................................... 37 tab le 4. sni signals ............................................................................................................................................................. 38 table 5. tail tag rules ......................................................................................................................................................... 42 table 6. fid+da look - up in the vlan mode ...................................................................................................................... 43 table 7. fid+sa look - up in the vlan mode ...................................................................................................................... 44 table 8. spi connections ..................................................................................................................................................... 47 table 9. mii management interface frame format .............................................................................................................. 49 table 10. serial management interface (smi) frame format .............................................................................................. 49 table 11. data rate selection in 100bt ............................................................................................................................... 90 table 12. data rate selection in 10bt ................................................................................................................................ . 90 table 13. format of static mac table for read (32 entries) ............................................................................................... 92 table 14. format of static mac table for writes (32 entries) ............................................................................................. 93 table 15. format of static vlan table (support max 4096 vlan id entries and 128 active v lans) ............................... 94 table 16. vlan id and indirect registers ............................................................................................................................ 95 table 17. format of dynamic mac address table (1k entries) .......................................................................................... 96 table 18. all port dropped packet mib counters ................................................................................................................. 99 table 19. format of all dropped packet mib counters ...................................................................................................... 100 table 20. eeprom timing parameters ............................................................................................................................. 109 table 21. sni timing parameters ....................................................................................................................................... 110 table 22. mac mode mii timing parameters ..................................................................................................................... 111 table 23. phy mode mii timing parameters ..................................................................................................................... 112 table 24. spi input timing parameters .............................................................................................................................. 113 table 25. spi output timing parameters ........................................................................................................................... 114 table 26. auto - negotiation timing parameters .................................................................................................................. 115 table 27. reset timing parameters ................................................................................................................................... 116 table 28. transformer selection criteria ............................................................................................................................ 118 table 29. qualified magnetic vendors ................................................................................................................................ 118 table 30. typical reference crystal characteristics .......................................................................................................... 118 april 1, 2014 14 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub pin configuration nc vddat nc nc 33 34 35 36 37 38 KSZ8895MLub (top view) nc pmrxdvnc nc nc nc nc nc pwrdn_n intr_n gndd vddc pmtxen pmtxd3 pmtxd2 pmtxd1 pmtxd0 pmtxer pmtxc gndd pmrxd1vddio pmrxc pmrxd3 pmrxd2 6362 61 60 59 58 57 56 55 54 53 52 51 50 4948 47 46 45 44 4342 41 40 39 64 nc led3-1 led4-0 led3-2sconf1 scol smrxd2 vddio smtxc smtxd0smtxd2 smtxen pcolpcrs pmrxer led4-1led4-2 led5-1 led5-2 vddc gndd sconf0scrs smrxd0 smrxd1 smrxd3smrxdv smrxc gndd smtxer smtxd1 smtxd3 pmrxd0 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 led2-1 led2-2 vddio gndd led3-0 101 100 99 98 97 led2-0 102 103 gnda led1-0 mdixdis test2 gnda in_pwr_sel ldo_o nc x2 x1 nc scanen testen vddc gndd rst_n ps0 ps1 spis_n spid/sda spic/scl spiq mdio mdc led1-1 led1-2 104105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 vddar rxp1 rxm1 gnda txp1 txm1 vddat rxp2 rxm2rxm3 txp3 rxp4 txm4 vddar nc gnda gnda txp2 txm2 vddar gnda iset vddat rxp3 gnda txm3 vddat rxm4 gnda txp4 gnda nc 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 nc led5-0 128 - pin lqfp april 1, 2014 15 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub pin description pin number pin name type (1) port pin function (2) 1 mdi - xdis ipd 1 ? 5 disable auto mdi/mdi - x. pd (default) = normal operation. pu = disable auto mdi/mdi - x on all ports. 2 gnda gnd analog ground. 3 vddar p 1.2v analog v dd . 4 rxp1 i 1 physical receive signal + (differe ntial). 5 rxm1 i 1 physical receive signal C (differential). 6 gnda gnd analog ground. 7 txp1 o 1 physical transmit signal + (differential). 8 txm1 o 1 physical transmit signal C (differential). 9 vddat p 3.3v analog v dd . 10 rxp2 i 2 physical receive signal + (differential). 11 rxm2 i 2 physical receive signal C (differential). 12 gnda gnd analog ground. 13 txp2 o 2 physical transmit signal + (differential). 14 txm2 o 2 physical transmit signal C (differential). 15 vddar p 1.2v ana log v dd . 16 gnda gnd analog ground. 17 iset set physical transmit output current. pull - down with a 12. 4 k?1% resistor. 18 vddat p 3.3v analog v dd . 19 rxp3 i 3 physical receive signal + (differential). 20 rxm3 i 3 physical receive signal - (di fferential). 21 gnda gnd analog ground. 22 txp3 o 3 physical transmit signal + (differential). 23 txm3 o 3 physical transmit signal C (differential). 24 vddat p 3.3v analog v dd . 25 rxp4 i 4 physical receive signal + (differential). 26 rxm4 i 4 physical receive signal - (differential). 27 gnda gnd analog ground. 28 txp4 o 4 physical transmit signal + (differential). 29 txm4 o 4 physical transmit signal C (differential). 30 gnda gnd analog ground. 31 vddar p 1.2v analog v dd . 32 nc nc no connect. 33 nc nc no connect. 34 gnda gnd analog ground. 35 nc nc no connect. 36 nc nc no connect. 37 vddat p 3.3v analog v dd . april 1, 2014 16 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub pin description (continued) pin number pin name type (1) port pin function (2) 38 nc nc no connect . 39 nc nc no connect. 40 nc nc no connect. 41 nc nc no connect. 42 nc nc no connect. 43 nc nc no connect. 44 nc nc no connect. 45 nc nc no connect. 46 nc nc no connect. 47 pwrdn_n ipu full - chip power down. active low. 48 intr_n opu interrupt. this pin is open - drain output pin . 49 gndd gnd digital ground. 50 vddc p 1.2v digital core v dd . 51 pmtxen ipd 5 reserved for mlub . no connect. 52 pmtxd3 ipd 5 reserved for mlub . no connect. 53 pmtxd2 ipd 5 reserved for mlub . no conne ct. 54 pmtxd1 ipd 5 reserved for mlub . no connect. 55 pmtxd0 ipd 5 reserved for mlub . no connect. 56 pmtxer ipd 5 reserved for mlub . no connect. 57 pmtxc i/ o 5 reserved for mlub . no connect. 58 gndd gnd digital ground. 59 vddio p 3.3v , 2.5v or 1.8 v digital v dd for digital i/o circuitry. 60 pmrxc i/ o 5 reserved for mlub . no connect. 61 pmrxdv ipd/o 5 reserved for mlub . no connect. 62 pmrxd3 ipd/o 5 reserved for mlub . strap option: pd (default) = enable flow control . pu = disable flow control. 63 pmrxd2 i pd /o 5 reserved for mlub . strap option: pd (d efault) = disable back pressure . pu = enable back pressure. 64 pmrxd1 ipd/o 5 reserved for mlub . strap option: pd (default) = d rop excessive collision packets . pu = does not drop excessive colli sion packets. 65 pmrxd0 ipd/o 5 reserved for mlub . strap option: pd (default) = disable aggressive back - off algorithm in half - duplex mode . pu = enable for performance enhancement. 66 pmrxer ipd/o 5 reserved for mlub . s trap option: pd (default) = 1522/1518 bytes; pu = packet size up to 1536 bytes. april 1, 2014 17 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub pin description (continued) pin number pin name type (1) port pin function (2) 67 pcrs ipd/o 5 reserved for mlub . strap option for port 4 only. pd (default) = force half - duplex if auto - negotiation is disab led or fails. pu = force full - duplex if auto negotiation is disabled or fails. refer to register 76. 68 pcol ipd/o 5 reserved for mlub . strap option for port 4 only. pd (default) = no force flow control, normal operation. pu = force flow control. refe r to register 66 . 69 smtxen ipd port 5 switch mii transmit enable. 70 smtxd3 ipd port 5 switch mii transmit bit 3. 71 smtxd2 ipd port 5 switch mii transmit bit 2. 72 smtxd1 ipd port 5 switch mii transmit bit 1. 73 smtxd0 ipd port 5 switch mi i transmit bit 0. 74 smtxer ipd port 5 switch mii transmit error. 75 smtxc i/o port 5 switch mii transmit clock: input: sw5 - mii mac mode . output: sw5 - mii phy modes. 76 gndd gnd digital ground. 77 vddio p 3.3v , 2.5v or 1.8 v digital v dd for digit al i/o circuitry. 78 smrxc i/o port 5 switch mii receive clock: input: sw5 - mii mac mode. output: sw5 - mii phy mode . 79 smrxdv i pd /o switch mii receive data valid. 80 smrxd3 i pd /o port 5 switch mii receive bit 3. strap option: pd (default) = disable switch sw5 - mii full - duplex flow control pu = enable switch sw5 - mii full - duplex flow control. 81 smrxd2 ipd/o port 5 switch mii receive bit 2. strap option: pd (default) = switch sw5 - mii in full - duplex mode; pu = switch sw5 - mii in half - duplex mode. 82 smrxd1 ipd/o port 5 switch mii receive bit 1. strap option: pd (default) = port 5 switch sw5- mii in 100mbps mode; sw5 - tmii in 2 00mbps mode . pu = switch sw5 - mii in 10mbps mode. 83 smrxd0 ipd/o port 5 switch mii receive bit 0 . strap option: led mod e pd (default) = mode 0; pu = mode 1. see register 11. mode 0, link at 100/full ledx[2,1,0]=0,0,0 100/half ledx[2,1,0]=0,1,0 10/full ledx[2,1,0]=0,0,1 10/half ledx[2,1,0]=0,1,1 mode 1, link at 100/full ledx[2,1,0]=0,1,0 100/half ledx[2,1,0]=0,1,1 10/full ledx[2,1,0]=1,0,0 10/half ledx[2,1,0]=1,0,1 mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act ledx_0 speed full duplex 84 scol ipd/o port 5 switch mii collision detec t: input: sw5 - mii mac modes. output: sw5 - mii phy modes. april 1, 2014 18 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub pin description (continued) pin number pin name type (1) port pin function (2) 85 scrs ipd/o port 5 switch mii modes carrier sense: input: sw5 - mii mac modes. output: sw5 - mii phy modes. 86 sconf1 ipd pin 91,86,87 are d ual mii configuration pin s for the port5 mac5 mii . sw5 - mii supports both mac mode and phy modes. pin# : (91, 86, 87) port5 switch mac5 sw5 - mii 000 disable, otri 001 phy mode mii 010 mac mode mii 011 phy mode s ni 100 disable (default) 101 phy mode mii 110 mac mode mii 111 phy mode sni 87 sconf0 i pd dual mii configuration pin. see pin 86 descriptions. 88 gndd gnd digital ground. 89 vddc p 1.2v digital core v dd . 90 led5 - 2 ipu /o 5 re served for mlub strap option: aging setup. see aging secti on. pu (default) = a ging enable pd = a ging disable. 91 led5 - 1 ipu/o 5 reserved for mlub strap option: pu (default): enable phy[5] mii i/f. pd: tristate and disable all phy[5] mii output. (d esign should pull this pin down as default for mlub . 92 led5 -0 ipu/o 5 reserved for mlub strap option for port 4 only. pu (default) = enable auto - negotiation. pd = disable auto - negotiation. strap to register76 bit[7] . 93 led4 -2 ipu/o 4 led indicator 2. 94 led4 -1 ipu/o 4 led indicator 1. 95 led4 -0 ipu/o 4 led indicator 0. strap option: pu (default) = normal mode . pd = energy detection mode (edpd mode). strap to register 14 bits[4:3] 96 led3 -2 ipu/o 3 led indicator 2. 97 led3 -1 ipu/o 3 led indicator 1. 98 led3 -0 ipu/o 3 led indicator 0. strap option: pu (default) = select i/o drive strength ( 8ma); pd = select i/o drive strength ( 12 ma). strap to register 132 bit[ 7-6 ]. 99 gndd gnd digital ground. 100 vddio p 3.3v , 2.5v or 1.8 v digital v dd for digital i/o circuitry. 101 led2 -2 ipu/o 2 led indicator 2. april 1, 2014 19 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub pin description (continued) pin number pin name type (1) port pin function (2) 102 led2 -1 ipu/o 2 led indicator 1. strap option: f or port 3 only. pu (default) = enable auto - negotiation. pd = disable auto - negotiation . strap to register60 bit[7]. 103 led2 -0 ipu/o 2 led indicator 0. 104 led1 -2 ipu/o 1 led indicator 2. 105 led1 -1 ipu/o 1 led indicator 1. strap option: for port 3 only. pu (default) = no force flow control, normal operatio n. pd = force flow control. strap to register60 bit[4] . 106 led1 -0 ipu/o 1 led indicator 0. strap option for port 3 only. pu (default) = force half - duplex if auto - negotiation is disabled or fails. pd = force full - duplex if auto negotiation is disabled or fails. strap to register60 bit[5]. 107 mdc ipu all switch mii management data clock. or smi interface clock . 108 mdio ipu/o all switch mii management data i/o. or smi interface data i/o. features internal pull down to define pin state when not drive n. need an external pull - up when driven. 109 spiq ipu/o all spi seria l data output in spi slave mode. 110 spic/scl ipu/o all spi slave mode: clock input (1) input clock up to 2 5mhz in spi slave mode , (2) output clock at 61khz in i 2 c master mode. see pin 113. 111 sspid/sda i pu /o all spi slave mode: serial data input . (1) serial data input in spi slave mode; (2) serial data input/output in i 2 c master mode. see pin 113. 112 spis_n i pu all spi slave mode: chip select (active low ). (1) spi data transfe r start in spi slave mode. when spis_n is high, the KSZ8895MLub is deselected and spiq is held in high impedance state, a high - to - low transition to initiate the spi data transfer. (2) not used in i 2 c master mode. 113 ps1 ipd serial bus configuration pin . for this case, if the eeprom is not present, the KSZ8895MLub will start itself with the ps[1.0] = 00 default register values. pin configuration serial bus configuration ps[1.0]=00 i 2 c master mode for eeprom ps[1.0]=01 smi interface mode ps[1.0]=10 spi slave mode for cpu interface ps[1.0]=11 factory test mode (bist) 114 ps0 ipd serial bus configuration pin. see pin 113. 115 rst_n ipu reset the KSZ8895MLub device . active low. 116 gndd gnd digital ground. 117 vddc p 1.2v digital core v dd . 118 testen ipd nc for normal operation. factory test pin. 119 scanen ipd nc for normal operation. factory test pin. 120 nc nc no connect. april 1, 2014 20 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub pin description (continued) pin number pin name type (1) port pin function (2) 121 x1 i 25 mhz crystal clock connection/or 3.3v o scillator input. crystal/ oscillator should be 5 0ppm tolerance . 122 x2 o 25mhz crystal clock connection. 123 nc nc no connect. 124 nc nc no connect. 125 ldo_o p ldo_o pin connect to gate pin of mosfet if using the internal 1.2v ldo controller. ldo_o pin will be floating if using an external 1.2v ldo. note: when pin126 voltage is greater than the internal 1.2v ldo controller enable threshold (1v), the internal 1.2v ldo controller is enabled and create s a 1.2v output when using an external mos fet. when pin126 is pull - down, the internal 1.2v ldo controller is disabled and pin 125 tri - stated. 126 in_pwr_sel i pull- up or a resistor divider: e nable internal 1.2v ldo controller. pull- down : d isable internal 1.2v ldo controller . note: a 4k pull - up and a 2k pull - down resistors divider network is recommended if using the internal 1.2v ldo controller and an external mosfet for 1.2v power. a 100 (approximately) resistor between the source and drain pins on the mosfe t is highly recommended as well. you can also use an external 1.2v ldo for 1.2v power supply. 127 gnda gnd analog ground. 128 test2 nc nc for normal operation. factory test pin. notes: 1. p = power supply. i = input. o = output. i/o = bidirecti onal. gnd = ground. ipu = input w/internal pull - up. ipd = input w/internal pull - down. ipd /o = input w/internal pull - down during reset, output pin otherwise. ipu /o = input w/internal pull - up during reset, output pin otherwise. nc = no connect. 2. pu = strap pin pull - up. pd = strap pull - down. otri = output tristated. april 1, 2014 21 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub pin for strap-in options the KSZ8895MLub can function as a managed switch or unmanaged switch. if no eeprom or micro - controller exists, the KSZ8895MLub will operate from its default setting. the strap - in option pins can be configures by external pull - up/down resistors and take the effect after power - down reset or warm reset, the functions are described in the following tables . pin number pin name pu/pd (1) description (2) 1 mdi - xdis ipd disable auto mdi/mdi - x. pd = (default) = normal operation pu = disable auto mdi/mdi - x on all ports. 62 pmrxd3 ipd/o strap option: pd (default) = enable flow control; pu = disable flow control. 63 pmrxd2 ipd/o strap option: pd (default) = disable back pressure; pu = enable back pressure. 64 pmrxd1 ipd/o strap option: pd (default) = drop excessive collision packets; pu = does not drop excessive collision packets. 65 pmrxd0 ipd/o strap option: pd (default) = disable aggressive back - off algorithm in half - duplex mode; pu = enable for performance enhancement. 66 pmrxer ipd/o strap option: pd (default) = 1522/1518 bytes; pu = packet size up to 1536 bytes. 67 pcrs ipd/o strap option for port 4 only. pd (default) = force half - duplex if auto - negotiat ion is disabled or fails. pu = force full - duplex if auto - negotiation is disabled or fails. refer to register 76. 68 pcol ipd/o strap option for port 4 only. pd (default) = no force flow control. pu = force flow control. refer to register 66. 80 smrxd3 ipd/o switch mii receive bit 3. strap option: pd (default) = disable switch sw5 - mii full - duplex flow control; pu = enable switch sw5 - mii full - duplex flow control. 81 smrxd2 ipd/o switch mii receive bit 2. strap option: pd (default) = switch sw5 - mii in full - duplex mode; pu = switch sw5 - mii in half - duplex mode. 82 smrxd1 ipd/o switch mii receive bit 1. strap option: pd (default) = switch sw5 - mii in 100mbps mode and sw5 - tmii in 200mbps pu = switch mii in 10mbps mode. 83 smrxd0 i pd /o switch mii receiv e bit 0. strap option: led mode pd (default) = mode 0; pu = mode 1. see register 11. mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act ledx_0 speed fulld april 1, 2014 22 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub pin for strap-in options (continued) pin number pin n ame pu/pd (1) description (2) 86 sconf1 ipd pin s 91, 86, 87 are d ual mii configuration pin s for the port5 mac5 mii . sw5 - mii supports both mac mode and phy modes. pin# : (91, 86, 87) port5 switch mac5 sw5 - mii 000 disable, otri 001 phy mode mii 010 mac mode mii 011 phy mode sni 100 disable 101 phy mode mii 110 mac mode mii 111 phy mode sni 87 sconf0 ipd dual mii configuration pin. see pin 86 descriptions. 90 led5 - 2 ipu/o strap option: aging setup. see aging section pu (default) = aging enable; pd = aging disable. 91 led5 - 1 ipu/o strap option: pu (default): enable phy[5] mii i/f. pd: tristate all phy[5] mii output. see pin 86 sconf1. 92 led5 -0 ipu/o strap option for port 4 only. pu (default) = enable aut o- negotiation. pd = disable auto - negotiation . strap to register76 bit[7] 95 led4-0 ipu/o led indicator 0. strap option: pu (default) = normal mode . pd = energy detection mode (edpd mode). strap to register 14 bits[4:3] 98 led3 -0 ipu/o led 3 indicator 0 . strap option: pu (default) = select i/o current drive strength ( 8ma); pd = select i/o current drive strength ( 12 ma). strap to register132 bit[7:6]. 102 led2 -1 ipu/o led 2 indicator 1. strap option for port 3 only. pu (default) = enable auto - negotiation. pd = disable auto - negotiation . strap to register60 bit[7 ] 105 led1 -1 ipu/o led 1 indicator 1. strap option for port 3 only. pu (default) = no force flow control, normal operation. pd = force flow control. strap to register50 bit[4] april 1, 2014 23 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub pin for strap-in options (continued) pin number pin name pu/pd (1) description (2) 106 led1 -0 ipu/o led 1 indicator 0. strap option for port 3 only. pu (default) = force half - duplex if auto - negotiation is disabled or fails. pd = force full - duplex if auto negotiation is disabled or fails. strap to register60 bit[5] . 113 ps1 ipd serial bus configuration pin. for this case, if the eeprom is not present, the KSZ8895MLub will start itself with the ps[1:0] = 00 default register values. pin configuration serial bus co nfiguration ps[1:0]=00 i 2 c master mode for eeprom ps[1:0]=01 smi interface mode ps[1:0]=10 spi slave mode for cpu interface ps[1:0]=11 factory test mode (bist) 114 ps0 ipd serial bus configuration pin. see pin 113. notes: 1. ipu = i nput w/internal pull - up. ipd = input w/internal pull - down. ipd /o = input w/internal pull - down during reset, output pin otherwise. ipu /o = input w/internal pull - up during reset, output pin otherwise. 2. pu = strap pin pull - up. pd = strap pull - down. april 1, 2014 24 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub introduction the KSZ8895MLub contains four 10/100 physical layer transceivers and five media access control (mac) units with an integrated layer 2 managed switch. the device runs in two modes. the first mode is as a 4- port integrated switch. the second is a s a 4- port switch with the fifth mac . in this mode, access to the fifth mac is provided through a media independent interface (mii). the KSZ8895MLub has the flexibility to reside in a managed or unmanaged design. in a managed design, a host processor has complete control of the KSZ8895MLub via the spi bus, or via the mdc/mdio interface with smi mode. an unmanaged design is achieved through i/o strapping or eeprom programming at system reset time. on the media side, the KSZ8895MLub supports ieee 802.3 10bas e- t, 100base - tx on all ports with auto mdi/mdix. the KSZ8895MLub can be used as fully - managed 4- port standalone switch or hook up to microprocessor by its sw - mii interface for an application solution. physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. there are a number of major enhancements from the ks8995ma to the KSZ8895MLub . these include: more host int erface options, four queues prioritization, tag as well as port based vlan, rapid spanning t ree support, igmp snooping support, port mirroring support and more flexible rate limiting and filtering functionalit y. physical layer transceiver 100base - tx transm it the 100base - tx transmit function performs parallel - to - serial conversion, 4b/5b coding, scrambling, nrz - to - nrzi conversion, mlt3 encoding and transmission. the circuit starts with a parallel - to - serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then co nverted into 4b/5b coding followed by a scrambler. the serialized data is further converted from nrz - to - nrzi format, and then transmitted in mlt3 current output. the output current is s et by an external 1% 12.4k resistor for the 1:1 transformer ratio. it has a typical rise/fall time of 4ns and complies with the ansi tp - pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave - shaped 10base - t output is also incorporated into the 100base - tx transmitter. 100base - tx receive the 100base - tx receiver function performs adaptive equalization, dc restoration, mlt3 - to - nrzi conversion, data and clock recovery, nrzi - to - nrz conversion, de - scrambling, 4b/5b decoding, and serial - to - parallel conversion. the receiving side starts with the equalization filter to compensate for inter - symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the length of the cabl e, the equalizer has to adjust its chara cteristics to optimize the performance. in this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. this is an ongoing process and can self - adjust against environmental changes such as temperature variations. the equalized signal then goes through a dc restoration and data conversion block. the dc restoration circ uit is used to compensate for the effect of baseline wander and improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. the signal is then sent through the de - scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and provided as the input data t o the mac. pll clo ck synthesizer the KSZ8895MLub generates 125mhz, 83mhz, 41mhz, 25mhz and 10mhz clocks for system timing. internal cloc ks are generated from an external 25mhz crystal or oscillator. scrambler/de - scrambler (100base - tx only) the purpose of the scrambler is to spread the power spectrum of the signal in order to reduce emi and baseline wander. the data is scrambled through the use of an 11 - bit wide linear feedback shift register (lfsr). this can generate a 2047 - bit non - repetitive sequence. the receiver will then de - scramble the incoming data stream with the same sequence at the transmitter. 10base - t transmit the output 10base - t driver is incorporated into the 100base - t driver to allow transmission with the same magnetics. they are internally wave - shaped and pre -e mphasized into outputs with typical 2.3v amplitude. the harmonic contents are at least 27db below the fundamental when driven by an all - ones manchester - encoded signal. april 1, 2014 25 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub 10base - t receive on the receive side, input buffer and level detecting squelch circuits are employed. a differential input receiver circuit and a pll perform the decoding function. the manchester - encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with s hort pulse widths in order to prevent noises at the rxp or rxm input from falsely triggering the decoder. when the input exceeds t he squelch limit, the pll locks onto the incoming signal and the KSZ8895MLub decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. mdi/mdi - x auto crossover to eliminate the need for crossover cables between similar devices, the KSZ8895MLub supports hp auto mdi/mdi - x and ieee 802.3u standard mdi/mdi - x auto crossover. hp auto mdi/mdi - x is the default. the auto - sense function detects remote transmit and receive pairs and correctly assigns transmit and recei ve pairs for the KSZ8895MLub device. this feature is extremely useful when end users are unaware of cable typ es, and also, saves on an additional uplink configuration connection. the auto - crossover feature can be disabled through the port control registers, or miim phy registers. the ieee 802.3u standard mdi and mdi - x definitions are highlighted in table 1: table 1. mdi/mdi - x pin definitions mdi mdi -x rj - 45 pins signals rj - 45 pins signals 1 td+ 1 rd+ 2 td - 2 rd - 3 rd+ 3 td+ 6 rd - 6 td - straight cable a straight cable connects an mdi device to an mdi - x device, or an mdi - x device to an mdi device. figure 1 depi cts a typical straight cable connec tion between a nic card (mdi) and a switch, or hub (mdi - x). figure 1 . typical straight cable connection april 1, 2014 26 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi - x device to another mdi - x device. figure 2 shows a typical crossover cable connection between two switches or hubs (two mdi - x devices). figure 2 . typical crossover cable connection auto - negotiation the KSZ8895MLub conforms to the auto - negotiation protocol as described by the 802.3 committee. auto - negotiation allows unshielded twisted pair (utp) link partners to select the highest common mode of operation. link par tners advertise their capabilities to each other, and then compare their own capab ilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selecte d as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest. ? highest : 100base - tx, full - duplex ? high: 100base - tx, half - duplex ? low: 10base - t, full - duplex ? lowest: 10base - t, half - duplex if auto - negotiation is not supported or the KSZ8895MLub link partner is forced to bypass auto - negotiation , the KSZ8895MLub sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allows the KSZ8895MLub to establish link by listening for a fixed signal protocol in the absence of auto - negotiation advertisement p rot ocol. the auto - negotiation link - up process is shown in figure 3. april 1, 2014 27 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub figure 3 . auto - negotiation april 1, 2014 28 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub linkmd ? cable diagnostics the linkmd ? feature utilizes time domain reflectometry (tdr) to analyze the cabli ng plant for common cabling problems such as open circuits, short circuits and impedance mismatches. linkmd ? works by sending a pulse of known amplitude and duration down the mdi and mdi - x pairs and then analyzes the shape of the reflected signal. timing the pulse duration gives an indication of the distance to the cab ling fault with maximum distance of 200m and accuracy of 2m. internal circuitry displays the tdr i nformation in a user - readable digital format. note: cable diagnostics are only valid for copper connections and do not support fiber optic operati on. access linkmd ? is initiated by accessing the phy special control/status registers {26, 42, 58, 74, 90} and the linkmd result registers { 27 , 43, 59, 75, 91} for ports 1, 2, 3, 4 and 5 respectively; and in conjunction with the registers port control 12 and 13 for ports 1, 2, 3, 4 and 5 respectively to disable auto - negotiation and auto mdi/mdix . alternatively, the miim phy registers 0 and 1d can be used for linkmd ? access also . usage the following is a sample procedure for using linkmd ? with registers {26, 27, 28, 29} on port 1. 1. disable auto - negotiation by writing a 1 to register 2 8 (0x1c) , bit [ 7]. 2. disable auto mdi/mdi - x by writing a 1 to register 29 (0x1d), bit [2] to enable manual control over the differential pair used to transmit the linkmd ? pulse. 3. a software sequence set up to the internal registers for linkmd only, see an example below. 4. start cable diagnostic test by writing a 1 to register 26 (0x1a) , bit [4]. this enable bit is self - clearing. 5. wait (poll) for register 26 (0x1a) , bit [4] to return a 0, and indicating cable diagnostic test is completed. 6. read cable diagnostic test results in register 26 (0x1a) , bits [6:5]. the results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) the 11 case, invalid test, occurs when the ksz8895 is unable to shut down the link partner. in t his instance, the test is not run, since it would be impossible for the ksz8895 to determine if the detected signal is a reflection of the signal generated or a signal from another source. 7. get distance to fault by concatenating register 26 (0x1a) , bit [0] and register 27 (0x1b) , bits [7:0]; and multiplying the result by a constant of 0.4. the distance to the cable fault can be determined by the following formul a: d (distance to cable fault) = 0.4 x { (register 26, bit [0]),(register 27, bits [7:0]) } d (distance to cable fault) is expressed in meters. concatenated value of registers 26 bit [0] and 27 bit [7:0] should be converted to decimal before decrease 26 and multiplying by 0.4. the constant (0.4) may be calibrated for different cabling conditions, including cables wit h a velocity of propagation that varies significantly from the norm. for port 2, 3, 4, 5 and for the miim phy registers, linkmd ? usage is similar. april 1, 2014 29 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub a linkmd example the following is a sample procedure for using linkmd ? on port 1. //set force 100/full and force mdix mode //w is write the register. r is read register w 1c ff w 1d 04 //set internal registers temporary adjustment for linkmd w 47 b0 w 27 00 w 37 03 (03 - port 1, 04 - port2, 05 - port3, 06 - port4, 07 - port5) w 47 80 (bit7 - port1, bit6 - port2, bit5 - port3, bit4 - port4, bit3 - port5) w 27 00 w 37 00 //enable linkmd testing with fault cable for port 1 w 1a 10 r 1a r 1b //result analysis based on the values of the r egister 0x1a and 0x1b for port 1: //the register 0x1a bits [6 - 5] are for the open or the short detection. //the register 0x1a bit [0] + the register 0x1b bits [7 - 0] = vct_fault [8 - 0] //the distance to fault is about 0.4 x {vct_fault [8 - 0] C 26} note: after end the testing, set all registers above to their default valu e, the default values are 00 for the reg ister (0x37) and the register (0x47) on - chip termination resistors the KSZ8895MLub reduces board cost and simplifies board layout by using on - chip termination resistors for all ports and the rx/tx differential pairs without the external termination resisto rs. the solution of the on chip termination and internal biasing will save about 50% power consumption compare with using external biasing and termination resistors, and the transformer will not consume power any more. internal 1.2v ldo controller the ksz8 895mlub reduces board cost and simplifies board layout by integrating a n internal 1.2v ldo controller to drive a low cost mosfet to supply the 1.2v core power voltage for a single 3.3v power supply solution . april 1, 2014 30 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub power management the KSZ8895MLub supports a fu ll - chip hardware power - down mode. when pwrdn pin 47 (p in pwrdn =0) is activated low, the entire chip is powered down. if this pin is de - asserted, the chip will be internally reset. the KSZ8895MLub can also use multiple power level of 3.3v, 2.5v or 1.8v fo r vddio to support different i/o voltage. the KSZ8895MLub supports enhanced power management feature in low power state with energy detection to ensure low - power dissipation during device idle periods. there are five operation modes under the power management function which is controlled by the register 14 bit [4:3] and the port register control 13 bit 3 as shown below: ? register 14 bit [4:3 ] = 00 normal operation mode ? register 14 bit [4:3 ] = 01 energy detect mode ? register 14 bit [4:3 ] = 10 soft power down mode ? register 14 bit [4:3 ] = 11 power saving mode ? port register 29, 45 , 61, 77, 93 control 13 bit 3 =1 are for the port based power - down mode table 2 indicates all internal function blocks status under four different power management operati on modes. tab le 2 . internal function block status KSZ8895MLub function blocks power management operation modes normal mode power - saving mode energy detect mode soft power - down mode internal pll clock enabled enabled disabled disabled tx/rx p hy enabled rx unused block disabled energy detect at rx disabled mac enabled enabled disabled disabled host interface enabled enabled disabled disabled normal operation mode this is the default setting bit [ 4:3 ] =00 in r egister 14 after the chip power - up or hardware reset. when KSZ8895MLub is in this normal operation mode, all pll clocks are running, phy and mac are on and the host int erface is ready for cpu read or write. during the normal operation mode, the host cpu can set the bit [ 4:3 ] in r egiste r 14 to transit the current normal operation mode to any one of the other three power management operation modes. energy detect mode the energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8895MLub is no t connected to an active link partner. in this mode, the device will save more power based o n the regular less power consumption. if the cable is not plugged , the KSZ8895MLub can automatically enter to a low power state, otherwise known as the energy detect mode. in this mode, KSZ8895MLub will keep transmitting 120ns width pulses at 1 pulse/s rate. once activity resumes due to plugging a cable or at tempting by the far end to establish link, the KSZ8895MLub can automatically power up to normal power state in energy detect mode. energy detect mode consists of two states, normal power state and low power state. while in low power state, the KSZ8895MLub reduces power consumption by disabling all circuitry except the energy detect cir cuitry of the receiver. the energy detect mode is entered by setting bit [ 4:3 ] =01 in register 14 . when the KSZ8895MLub is in this mode, it will monitor the cable energy. if there is no energy on the cable for a time longer than pre - configured value at bit [7:0] go - sleep time in regis ter 15 , KSZ8895MLub will go into a low power state. when KSZ8895MLub is in low power state, it will keep monitoring the cable energy. once the energy is detected from the cable , KSZ8895MLub will enter normal power state . when KSZ8895MLub is at normal power state, it is able to transmit or receive packet from the cable. april 1, 2014 31 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub soft power - down mode the soft power - down mode is entered by setting bit [4:3] =10 in register 14 . when KSZ8895MLub is in this mode, all pll clocks are disabled, also all of phys and the macs are off. any dummy host access will wake - up this device from current soft power - down mode to normal operation mode and internal reset will be issued to make all internal registers go to the default values. power - saving mode the power saving mode is entered when auto - negotiation mode is enabled, cable is disconnected, and by setting bit [4:3] =11 in register 14 . when KSZ8895MLub is in this mode, all pll clocks are enabled, mac is on, all internal registers value will not change, and host interface is ready for cpu read or write. in this mode, i t mainly controls the phy transceiver on or off based on line status to achieve power saving. the phy remains transmitting and only turns off the unused receiver block. once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8895MLub can automatically enabled the phy power up to normal power state from power saving mode. during this power - saving mode, the host cpu can set bit [4:3] in register 14 to transit the current power saving mode to any one of the other three power management operation modes. port - based power - down mode in addition, t he KSZ8895MLub features a per - port power down mode. to save power, a phy port that is not in use can be powered down via the port registers control 13 bit3, or miim phy registers 0 bit11. switch core address look - up the internal look - up table stores mac addresses and their associated information. it contains a 1k unicast address table plus switching information. the KSZ8895MLub is guaranteed to learn 1k addresses and distinguishes itself from a hash - based look - up table, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. learning the internal look - up engine updates its table with a new entry if the following conditions are met: ? the received packets source address (sa) does not exist in the look - up table. ? the received packet is good; the packet has no receiving errors and is of legal length. the look - up engine inserts the qualified sa into the table, along with the port number and time stamp. if the table is full, the last entry of the table is deleted first to make room for the new entry. migration the internal look - up engine also monitors whether a station is moved. if this occurs, it updates the ta ble accordingly. migration happens when the following conditions are met: ? the received packets sa is in the table but the associated source port information is diff erent. ? the received packet is good; the packet has no receiving errors and is of legal length. the look - up engine will update the existing record in the table with the new source port information. aging the look - up engine will update the time stamp information of a record whenever the corresponding sa appears . the time stamp is used in the aging process. if a record is not updated for a period of time, the look - up engine will remove the record from the table. the look - up engine constantly performs the aging process and will continuously remove aging re cords. the aging period is 300 75 seconds. this feature can be enabled or disabled through register 3 or by external pull - up or pull - down resistors on led[5][2]. april 1, 2014 32 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub forwarding the KSZ8895MLub will forward packets using an algorithm that is depicted in the following f lowcharts. figure 6 shows stage one of the forwarding algorithm where the search engine looks up the vlan id , static table, and dynamic table for the destination address, and comes up with port to forward 1 (ptf1). ptf1 is then further m odified by the spanning tree, igmp snooping, port mirroring, and port vlan processes to come up with port to forward 2 ( ptf2), as shown in figure 7. this is where the packet will be sent. KSZ8895MLub will not forward the following packets: ? error packets. these include framing errors, fcs errors, alignment errors, and illegal si ze packet errors. ? 802.3x pause frames. the KSZ8895MLub will intercept these packets and perform the appropriate actions. ? local packets. based on destination address (da) look - up. if the destination port from the look - up table matches the port where the packet was from, the packet is defined as local. switching engine the KSZ8895MLub features a high - performance switching engine to move data to and from the macs, packet buffers. it operates in store and forward mode, while the efficient switching mechanism reduces overall lat ency. the KSZ8895MLub has a 64kb internal frame buffer. this resource is shared between all five ports. there ar e a total of 512 buffers available. each buffer is sized at 128 b. media access controller (mac) operation the KSZ8895MLub strictly abides by ieee 802.3 standards to maximize compatibility. inter - packet gap (ipg) if a frame is successfully transmitted, the 96 - bit time ipg is measured between the two consecutive mtxen. if the current packet is experiencing collision, the 96 - bit time ipg is measured from mcrs and the next mtxen. backoff algorithm the KSZ8895MLub implements the ieee standard 802.3 binary exponential backoff algorithm, and optio nal aggressive mode backoff. after 16 collisions, the packet will be optionally dropped, depending on the chip configuration in register 3. see register 3. late collision if a transmit packet experiences collisions after 512 - bit times of the transmission, the packet will be droppe d. illegal frames the KSZ8895MLub discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in register 4. for special applications, the KSZ8895MLub can also be programmed to accept frames up to 1916 bytes in register 4. since the KSZ8895MLub supports vlan tags, the maximum sizing is adjusted when these tags are present. flow control the KSZ8895MLub supports standard 802.3x flow control frames on both transmit and receive sides. on the receive side, if the KSZ8895MLub receiv es a pause control frame, the KSZ8895MLub will not transmit the next normal frame until the timer, specified in the pause control frame, expires. if a not her pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. during this period (being flow controlled), only flow control packets from the KSZ8895MLub will be transmitted. on the transmit side, the KSZ8895MLub has intelligent and efficient ways to determine when to invoke flow control . the flow control is based on availability of the system resources, including availabl e buffers, available transmit queues and available receive queues. the KSZ8895MLub flow controls a port that has just received a packet if the destination port resource is busy . the KSZ8895MLub issues a flow control frame (xoff), containing the maximum pause time defined in ieee st andard 802.3x. once the resource is freed up, the KSZ8895MLub sends out the other flow control frame (xon) with zero pause time to turn off the flow control (turn on transmission to the port). a hysteresis feature is also provided to prevent over - activation and deactivation of the flow control mechanism. the KSZ8895MLub flow controls all ports if the receive queue becomes full. april 1, 2014 33 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub figure 4 . destination address lookup flow chart (stage 1) april 1, 2014 34 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub figure 5 . destination address resolution flow chart (stage 2) the KSZ8895MLub will not forward the following packets: 1. error packets these include framing errors, frame check sequence (fcs) errors, alignment errors, and illegal size packet errors. 2. ieee802.3x pause frames KSZ8895MLub intercepts these packets and performs full duplex flow control accordingly. 3. "local" packets based on destination address (da) lookup , i f the destination port from the lookup table matches the port from which the packet originated, the packet is defined as "local." april 1, 2014 35 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub half - duplex back pressure the KSZ8895MLub also provides a half - duplex back pressure option (note: this is not in ieee 802.3 standards). the activation and deactivation conditions are the same as the ones given for full - duplex mode. if back pressure is required, the KSZ8895MLub sends preambles to defer the other station's transmission (carrier sense defer ence). to avoid jabber and excessive deference as defined in ieee 802.3 standards, after a certain period of time, the KSZ8895MLub discontinues carrier sense but raises it quickly after it drops packets to inhibit other transmissions. this short silent tim e (no carrier sense) is to prevent other stations from sending out packets and keeps other statio ns in a carrier sense - deferred state. if the port has packets to send during a back pressure situat ion, the carrier sense - type back pressure is interrupted and those packets are transmitted instead. if there are no more packets to send, carrier sens e - type back pressure becomes active again until switch resources are free. if a collision occurs, the binary expo nential backoff algorithm is skipped and carrier sense is generated immediately, reducing the c hance of further colliding and maintaining carrier sense to prevent reception of packets. to ensure no packet loss in 10base - t or 100base - tx half - duplex modes, the user must enable the following: ? aggressive backoff (register 3 , bit 0) ? no excessive collision drop (register 4, bit 3) ? back pressure (register 4, bit 5) these bits are not set as the default because this is not the ieee standard. broadcast storm protection the KSZ8895MLub has an intelligent option to protect the switch system from receiving too many broa dcast packets. broadcast packets are normally forwarded to all ports except the source port and thus use too many sw itch resources (bandwidth and available space in transmit queues). the KSZ8895MLub has the option to include multicast packets for storm control. the broadcast storm rate parameters are programmed globally and can be en abled or disabled on a per port basis. the rate is based on a 50ms (0.05s) interval for 100bt and a 500ms (0.5s) interval for 10bt . at t he beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the interval. the rate definition is described in registers 6 and 7. the default setting for regi sters 6 and 7 is 0x4a (74 decimal). this is equal to a rate of 1%, calculated as follows: 148,80 frames/sec x 50ms (0.05s)/interval x 1% = 74 frames/interval (approx.) = 0x4a mii interface operation the media independent interface (mii) is specified by the ieee 802.3 committee and provi des a common interface between physical layer and mac layer devices. the KSZ8895MLub provides such interfaces on port 5. the sw 5- mii interface is used to connect to the fifth mac. the mii interface contains two distinct groups of signals, one for transmission and the other for receiving. port 5 mac 5 sw5 - mii interface table 3 shows two connection manners: 1. the first is an external mac connects to sw 5- mii phy mode. 2. the second is an external phy connects to sw 5- mii mac mode. please see the pin s [91, 86, and 87] description for detail configuration for the mac mode and phy mode , sw 5- mii works with 25mhz and 2.5mhz clock for 100base - tx and 10base - t. april 1, 2014 36 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub table 3 . switch mac 5 mii signals KSZ8895MLub phy mode connections description KSZ8895MLub mac mode connections external mac KSZ8895MLub sw5- mii signal type external phy KSZ8895MLub sw5 - mii signal type mtxen smtxen input transmit enable mtxen smrxdv output mtxer smtxer input transmit error mtxer not used not used mtxd3 smtxd [3] input transmit data bit 3 mtxd3 smrxd[3] output mtxd2 smtxd[2] input transmit data bit 2 mtxd2 smrxd[2] output mtxd1 smtxd[1] input transmit data bit 1 mtxd1 smrxd[1] output mtxd0 smtxd[0] input transmit data bit 0 mtxd0 smrxd[0] output mtxc smtxc output transmit clock mtxc smrxc input mcol scol output collision detection mcol scol input mcrs scrs output carrier sense mcrs scrs input mrxdv smrxdv output receive data valid mrxdv smtxen input mrxer not used output receive error mrxer smtxer input mrxd3 smrxd[3] output receive data bit 3 mrxd3 smtxd[3] input mrxd2 smrxd[2] output receive data bit 2 mrxd2 smtxd[2] input mrxd1 smrxd[1] output receive data bit 1 mrxd1 smtxd[1] input mrxd0 smrxd[0] output receive data bit 0 mrxd0 smtxd[0] input mrx c smrxc output receive clock mrxc smtxc input the switch mii interface operates in either mac mode or phy mode for KSZ8895MLub . these interfaces are nibble - wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). additional signals on the trans mit side indicate when data is valid or when an error occurs during transmission. likewise, the recei ve side has indicators that convey when the data is valid and without physical layer errors. for half - duplex operation there is a signal that indicates a collision has occurred during transmission. note that the signal mrxer is not provided on the mii - sw interface for phy mode operation and the signal mtxer is not provided on the mii - sw interface for mac mode operation. normally mrxer would indicate a rec eive error coming from the physical layer device. mtxer would indicate a transmit error from t he mac device. these signals are not appropriate for this configuration. for phy mode operation, if the device interfacing with the KSZ8895MLub has a n mrxer pin, it should be tied low. for mac mode operation, if the device interfacing with the KSZ8895MLub has an mtxer pin, it should be tied low. sni interface operation the serial network interface (sni) is compatible with some controllers used for network layer protocol processing. this interface can be directly connected to these types of devices. the signals are divided into two groups, one for transmission and the other for reception. the signals involved are described in table 4. april 1, 2014 37 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub table 4 . sni signals sni signal description KSZ8895MLub signal txen transmit enable smtxen txd serial transmit data smtxd[0] txc transmit clock smtxc col collision detection scol crs carrier sense smrxdv rxd serial receive data smrxd[0] rxc receive clock smrxc this interface is a bit - wide data interface and therefore runs at the network bit rate (not encoded). an additional signal on the transmit side indicates when data is valid. likewise, the receive s ide has an indicator that conveys when the data is valid. for half - duplex operation there is a signal that indicates a collision has occurred during transmiss ion. april 1, 2014 38 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced functionality qos priority support the KSZ8895MLub provides quality - of - service (qos) for applications such as voip and video conferencing. the KSZ8895MLub offer 1/2/4 priority queues option per port by setting the port registers xxx control 9 bit1 and the port registers xxx control 0 bit0, the 1/2/4 queues split as follows, [port registers xxx control 9 bit1, control 0 bit 0]=00 single output queue as default. [port registers xxx control 9 bit1, control 0 bit0]=01 egress port can be split into two priority transmit queues. [port registers xxx control 9 bit1, control 0 bit0]=10 egress port can be split into four priority transmit queues. the four priority transmit queues is a new feature in the KSZ8895MLub . the queue 3 is the highest priority queue and queue 0 is the lowest priority queue. the port registers xxx control 7 bit1 and the port registers xxx control 0 bit0 are used to enable split transmit queues for ports 1, 2, 3, 4 and 5, respecti vely. if a port's transmit queue is not split, high prior ity and low priority packets have equal priority in the transmit queue. there is an additional option to either always deliver high priority packets first or use progr ammable weighted fair queuing for the four priority queues scale by the port registers control 1 0 , 1 1 , 1 2 and 13 (default value are 8, 4, 2, 1 by their bit[6:0]. register 130 bit[7:6] prio_2q[1:0] is used w hen the 2 q ueue configuration is selected, these bits are used to map the 2 - bit result of ieee 802.1p from the registers 128, 129 or tos/diffserv mapping from regist ers 144 - 159 (for 4 queues) into two queues mode with priority high or low. please see the descriptions of the register 130 bits [7:6] for detail. port - based priority with port - based priority, each ingress port is individually classified as a priori ty 0-3 receiving port. all packets received at the priority 3 receiving port are marked as high priority and are sent to the high - priority transmit queue if the corresponding transmit queue is split. the port registers control 0 bits [4:3] is used to enable port - based priority for ports 1, 2, 3, 4 and 5, respectively. 802.1p - based priority for 802.1p - based priority, the KSZ8895MLub examines the ingress (incoming) packets to determine whether they are tagged. if tagged, the 3 - bit priority field in the vlan tag is retrieved and compared against the priori ty mapping value, as specified by the registers 128 and 129 , both register 128/129 can map 3 - bit priority field of 0 - 7 value to 2 - bit result of 0 - 3 priority levels. the priority mapping value is programmable. the following figure illustrates how the 802.1p priority field is embedded in the 802.1q vlan tag. fig ure 6 . 802.1p priority field format april 1, 2014 39 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub 802.1p - based priority is enabled by bit [5] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively. the KSZ8895MLub provides the option to insert or remove the priority tagged frame's header at each individual egress port. this header, consisting of the 2 bytes vlan protocol id (vpid) and the 2 - byte tag control information field (tci), is also referred to as the ieee 802.1q vlan tag. tag insertion is enabled by bit [2] of the p ort registers control 0 and the port register control 8 to select which source port (ingress port) pvid can be inserted on the egress port for ports 1, 2, 3, 4 and 5, respectively. at the egress port, untagged packets are tagged with the ingress ports default tag. the default tags are programmed in the port registers control 3 and control 4 for ports 1, 2, 3, 4 and 5, respectively. the KSZ8895MLub will not add tags to already tagged packets. tag removal is enabled by bit [1] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively. at the egress port, tagged packets will have their 802.1q vlan tags removed. the KSZ8895MLub will not modify untagged packets. the crc is recalculated for both tag insertion and tag removal. 802.1p priority field re - mapping is a qos feature that allows the KSZ8895MLub to set the user priority ceiling at any ingress port by the port register control 2 bit 7. if the ingress packets priority fi eld has a higher priority value than the default tags priority field of the ingress port, the packets priority field is replaced with the default tags priori ty field. diffserv - based priority diffserv - based priority uses the tos registers (registers 144 to 159) in the advanced c ontrol registers section. the tos priority control registers implement a fully decoded, 128 - bit differentiated services code point (dscp) register to determine packet priority from the 6 - bit tos field in the ip header. when the most significant 6 bits of the tos field are fully decoded, the resultant of the 64 possibilities of dscp decoded is compared with the cor responding bits in the dscp register to determine priority. spanning tree support port 5 is the designated port for spanning tree support. the other ports (port 1 C port 4) can be configured in one of the five spanning tree states via transmit ena ble, receive enable, and learning disable register settings in registers 18, 34, 50, and 66 for ports 1, 2, 3, and 4, respectively. the following description shows the port setting and software actions taken for each of the five spa nning tree states. disable state: the port should not forward or receive any packets. learning is disabled. port setting: "transmit enable = 0, receive enable = 0, learning disable = 1." software action: the processor should not send any packets to the port. the sw itch may still send specific packets to the processor (packets that match some entries in the static table with over riding bit set) and the processor should discard those packets. note : p rocessor is connected to port 5 via mii interface. address learning is disabled on the port i n this state. blocking state: only packets to the processor are forwarded. learning is disabled. port setting: "transmit enable = 0, receive enable = 0, learning disable = 1" softwar e action: the processor should not send any packets to the port(s) in this state. the processor shou ld program the static mac table with the entries that it needs to receive (e.g., bpdu packets) . the overriding bit should also be set so that the switch will forward those specific packets to the processor. address learning is disabled on the port in this state. listening state: only packets to and from the processor are forwarded. learning is disabled. port setting: "transmit enable = 0, receive enable = 0, learning disable = 1. "software action: the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward t hose specific packets to the p rocessor. the processor may send packets to the port(s) in this state, see tail tagging mode section for details. address learning is disabled on the port in this state. learning state: only packets to and from the processor are forwarded. learning is en abled. port setting: transmit enable = 0, receive enable = 0, learning disable = 0. software action: the processor should program the static mac table with the entries t hat it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward thos e specific packets to the processor. the processor may send packets to the port(s) in this state, see tail tagging mode section for details. address learning is enabled on the port in this state. forwarding state: p ackets are forwarded and received normally. learning is enabled. april 1, 2014 40 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port setting: transmit enable = 1, receive enable = 1, learning disable = 0. software action: the processor should program the static mac table with the entries t hat it needs to receive (e.g., bpd u packets). the overriding bit should be set so that the switch will forward t hose specific packets to the processor. the processor may send packets to the port(s) in this state, see tail tagging mode section for details. address learning is enabled on the port in this state. rapid spanning tree support there are three operational states of the discarding, learning, and forwarding assigned to each port f or rstp: discarding ports do not participate in the active topology and do not learn mac addresses. discarding state: the state includs three states of the disable, blocking and listening of stp. port setting: "transmit enable = 0, receive enable = 0, learning disable = 1." software action: the processor should not send any packets to the port. the sw itch may still send specific packets to the processor (packets that match some entries in the static table with over riding bit set) and the processor should discard those packets. when disable the ports learning capability (learning disable= 1), set the register 1 bit5 and bi4 will flush rapidly with the port related entries in the dynamic mac table and static mac table. note : p rocessor is connected to port 5 via mii interface. address learning is disabled on the port i n this state. ports in learning states learn mac addresses, but do not forward user traffic. learning state: only packets to and from the processor are forwarded. learning is enabled. port setting: transmit enable = 0, receive enable = 0, learning disable = 0. software action: the proces sor should program the static mac table with the entries that it needs to receive (e. g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see tail tagging mode section for details. address learning is ena bled on the port in this state. ports in forwarding states fully participate in both data forwarding and mac learning. forwarding state: packets are forwarded and received normally. learning is enabled. port setting: transmit enable = 1, receive enable = 1, learning disable = 0. software action: the processor should program the static mac table with the entries t hat it needs to receive (e.g., bpdu packets). the overridin g bit should be set so that the switch will forward those specific packets t o the processor. the processor may send packets to the port(s) in this state, see tail tagging mode section for details. address learning is enabled on the port in this state. r stp uses only one type of bpdu called rstp bpdus. they are similar to stp configuration bpdus with the exception of a type field set to version 2 for rstp and version 0 for stp, and a flag field carrying additional information. tail tagging mode the tail tag is only seen and used by the port 5 interface, which should be connected to a processor by s w5 - mii interface. the one byte tail tagging is used to indicate the source/destinat ion port in port 5. only bit [3 - 0] are used for the destination in the tai l tag ging byte. other bits are not used. the tail tag feature is enabled by setting register 12 . figure 7 . tail tag frame format april 1, 2014 41 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub table 5 . tail tag rules ingress to port 5 (host ? > KSZ8895MLub ) bit [3:0] destination 0,0,0,0 reserved 0,0,0,1 port 1 (direct forward to port1) 0,0,1,0 port 2 (direct forward to port2) 0,1,0,0 port 3 (direct forward to port3) 1,0,0,0 port 4 (direct forward to port4) 1,1,1,1 port 1, 2,3 and 4 (direct forward to port 1,2,3,4,) bit [7:4] 0,0,0,0 queue 0 is used at destination port 0,0,0,1 queue 1 is used at destination port 0,0,1,0 queue 2 is used at destination port 0,0,1,1 queue 3 is used at destination port x, 1,x,x whatever send packets to specified port in b it[3:0] 1, x,x,x bit[6:0] will be ignored as normal (address look up) egress from port 5 ( KSZ8895MLub ? > host) bit [1:0] source 0,0 port 1 (packets from port 1) 0,1 port 2 (packets from port 2) 1,0 port 3 (packets from port 3) 1,1 port 4 (packets fr om port 4) igmp support there are two parts involved to support the internet group management protocol (igmp) in layer 2 . t he first part is igmp snooping, the second part is this igmp packet to be sent back to the subscribed port. describe t hem as follo ws. igmp snooping the KSZ8895MLub traps igmp packets and forwards them only to the processor (port 5 sw5 - mii/rmii ). the igmp packets are identified as ip packets (either ethernet ip packets, or iee e 802.3 snap ip packets) with ip version = 0x4 and protoc ol version number = 0x2. s et register 5 bit [6] to 1 to enable igmp snooping. igmp send back to the subscribed port once the host responds the received igmp packet, the host should know the original igmp ingress port and send back the igmp packet to this port only , otherwise this igmp packet will be broadcasted to all port to downgrade the performance. enable the tail tag mode, the host will know the igmp packet receive d port from tail tag bits [1:0] and can send back the response igmp packet to this subscribed port by setting the bits [3:0] in the t ail tag . enable tail tag mode by setting register 12 bit 1. april 1, 2014 42 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port mirroring support KSZ8895MLub supports port mirror comprehensively as: ? receive only mirror on a port all the packets received on the port will be mirrored on the sniffer port . for example, port 1 is programmed to be rx sniff, and port 5 is programmed to be the sniffer port. a packet, recei ved on port 1, is destined to port 4 after the internal look - up. the KSZ8895MLub will forward the packet to both port 4 and port 5. KSZ8895MLub can optionally forward even bad received packets to port 5. ? transmit only mirror on a port all the packets transmitted on the port will be mirrored on the sniffer port. for example, port 1 is programmed to be tx sniff, and port 5 is programmed to be the sniffer port. a packet, received on any of the ports, is destined to port 1 after the internal look - up. the KSZ8895MLub will forward the packet to both ports 1 and 5. ? receive and transmit mirror on two ports all the packets received on port a and transmitted on port b will be mirrored on the sn iffer port. to turn on the and feature, set register 5 bit 0 to 1. for example, port 1 is programmed to be rx sniff, port 2 is programmed to be transmit sniff, and port 5 is programmed to be the sniffer port. a packet, received on port 1, is destined to port 4 after the internal look - up. the KSZ8895MLub will forward the packet to port 4 only, since it does not meet the and condition. a packet, received on port 1, is destined to port 2 after the internal look - up. the KSZ8895MLub will forward the packet to both port 2 and port 5. multiple ports can be selected to be rx sniffed or tx sniffed. and any port can be selected to be the sniffer port. all the se per port features can be selected through register 17. vlan support KSZ8895MLub supports 128 active vlans and 4096 possible vids specified in ieee 802.1q. KSZ8895MLub provides a 128 - entry vlan table, which correspond to 4096 possible vids and converts to fid (7 bi ts) for address look - up max 128 active vlans. if a non - tagged or null - vid - tagged packet is received, the ingress port vid is used for look - up when 802.1q is enabled by the global register 5 control 3 bit 7. in the vlan mode, the look - up process starts from vlan table look - up to determine whether the vid is valid. if the vid is not valid, the packet wi ll be dropped and its address will not be learne d. if the vid is valid, fid is retrieved for further look - up by the static mac table or dynamic mac table . fid+da is used to determine the destination port. t he followed table describes the difference actions at different situations of da and fid+da in the static mac table and dynamic mac table after the vlan table finish a look - up action. fid+sa is use d for learning purposes. t he followed table also describes how to learning in the dynamic mac table when vlan table has done a look - up and the static mac table without a valid entry. table 6 . fid+da look - up in the vlan mode da found in static mac table use fid flag? fid match? da+fid found in dynamic mac table action no dont care dont care no broadcast to the membership ports defined in the vlan table bit [11:7]. no dont care dont care yes send to the destination port defined in the dynamic mac table bit [5 8 :5 6 ]. yes 0 dont care dont care send to the destination port(s) defined in the static mac table bit [52:48]. yes 1 no no broadcast to the membership ports defined in the vlan table bit [11:7]. yes 1 no yes send to the destination port defined in the dynamic mac table bit [5 8 :5 6 ]. yes 1 yes dont care send to the destination port(s) defined in the static mac table bit [52:48]. april 1, 2014 43 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub table 7 . fid+sa look - up in the vlan mode sa+fid found in dyna mic mac table action no the sa+fid will be learned into the dynamic table. yes time stamp will be updated. advanced vlan features are also supported in KSZ8895MLub , such as vlan ingress filtering and discard non pvid defined in bits [6:5] of the port register control 2. these features can be controlled on a port b asis. rate limiting support the KSZ8895MLub provides a fine resolution hardware rate limiting . the rate step is 64kbps when the rate limit is less than 1mbps rate for 100bt or 10bt. the rate step is 1mbps when the rate limit is more than 1mbps rate for 100bt or 10bt (refer to data rate selection table which follow the end of the port register queue 0 ? 3 ingress/egress limit control section). the rate limit is independently on the receive side and on the transmit side on a per port basis. for 10base - t, a rate setting above 10 mbps means the rate is not limited. on the receive side, the data rece ive rate for each priority at each port can be limited by setting up ingress rate control registers. on the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up egress rate control registers. the size of each frame has options to include minimum ifg (inter frame gap) or preamble b yte, in addition to the data field (from packet da to fcs). ingress rate limit for ingress rate limiting, KSZ8895MLub provides options to selectively choose frames from all types, multicast , broadcast, and flooded unicast frames by bits [3 ? 2] of the port rate limit control register. the KSZ8895MLub counts the data rate from those selected type of frames. packets are dropped at the i ngress port when the data rate exceeds the specified rate limit or the flow control takes effect without packet dropped when the ingress rate limit flow control is enabled by the port rate limit control register bit 4. the ingress rate limiting supports the port - based , 802.1p and diffserv - based priorit ies, the port - based priority is fixed priority 0 ? 3 selection by bits [4 ? 3] of the port register control 0. the 802.1p and diffserv - based priority can be mapped to priority 0 ? 3 by default of the register 128 and 129. in the ingress rate limit, set register 135 global control 19 bit3 for queue - based rate limit to be enabled if use two queues or four queues mode, all related ingress ports and egress port should be spitted to two queues or four queues mode by the port registers control 9 and control 0. the four queues mode will use q0 - q3 for priority 0 -3 by bit [6 - 0] of the port register ingress l imit control 1 ? 4 . the two queues mode will use q0 - q1 for priority 0 -1 by bit [6 - 0] of the port register ingress limit control 1 ? 2 . the priority level s in the packets of the 802.1p and diffserv can be programmed to priority 0 - 3 by the register 128 and 12 9 for a re - mapping. egress rate limit for egress rate limiting, the leaky bucket algorithm is applied to each output priority que ue for shaping output traffic. int er frame gap is stretched on a per frame base to generate smooth, non - burst egress traffic. t he throughput of each output priority queue is limited by the egress rate specified by the data rate select ion table followed the egress rate limit contro l registers. if any egress queue receives more traffic than the specified egress rate throu ghput, packets may be accumulated in the output queue and packet memory. after the memory of the queue or the port is used up, packet dropping or flow control will be triggered. as a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rat e. the egress rate limiting supports the port - based , 802.1p and diffserv - based priorit ies, the port - based priority is fixed priority 0 ? 3 selection by bits [4 ? 3] of the port register control 0. the 802.1p and diffserv - based priority can be mapped to priority 0 ? 3 by default of the register 128 and 129. in the e gress rate limit, set register 135 global control 19 bit3 for queue - based rate limit to be enabled if use two queues or four queues mode, all related ingress ports and egress port should be s pitted to two queues or four queues mode by the port registers control 9 and control 0. the four queues mode will use q0 - q3 for priority 0 ? 3 by bit [6 ? 0] of the port register egress limit control 1 ? 4 . the two queues mode will use q0 ? q1 for priority 0 ? 1 by bit [6 ? 0] of the port register egress limit control 1 ? 2 . april 1, 2014 44 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub the priority level s in the packets of the 802.1p and diffserv can be programmed to priority 0 ? 3 by t he register 128 and 129 for a re - mapping. when egress rate limit just use one queue per port for the egress port rate limi t, the priority packets will be based on the data rate selection table with the rate limit exact number. if egress rate limit us e more than one queue per port for the egress port rate limit, the highest priority packets will be based on the data rate selection table f or the rate limit exact number, other lower priority packet rate will be limited based on 8:4:2:1 (default) priority rati o based on the highest priority rate. the transmit queue priority ratio is programmable. to reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidt h. transmit queue ratio programming in transmit queues 0 ? 3 of the egress port, the default priority ratio is 8:4:2:1, the priority ratio can be program med by the port registers control 10, 11, 12 and 13. when the transmit rate exceed the rat io limit in the transmit queue, the transmit rate will be limited by the tr ansmit queue 0 ? 3 ratio of the port register control 10, 11, 12 and 13. the highest priority queue will be no limited, other lower priority queues will be limited based on the transm it queue ratio. filtering for self - address, unknown unicast/ m ulticast a dd ress and u nknown vid p acket/ip m ulticast enable self - address filtering , the unknown unicast packet filtering and forwarding by the r egister 131 global c ontrol 1 5 . enable unknown multicast packet filtering and forwarding by the r egister 132 global c ontrol 16. enable unknown vid packet filtering and forwarding by the r egister 133 global c ontrol 17 . enable unknown ip multicast packet filtering and forwarding by the r egister 134 global c ontrol 18 . this function is very useful in preventing those kind s of packets that could degrade the quality of the port in applications such as voice over internet protocol (voip) and the daisy chain connection to prevent packets into endless loop . april 1, 2014 45 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub configuration interfaces i 2 c master serial bus configuration if a 2 - wire eeprom exists, then the KSZ8895MLub can perform more advanced features like broadcast storm protection and rate control. the eeprom should have the entire valid configuration data from register 0 to regist er 255 defined in the memory map, except the chipid = 0 in the register1 and the status registers. after r eset, the KSZ8895MLub will start to read all 255 registers sequentially from the eeprom. the configuration access tim e (t prgm ) is less than 30ms, as shown in figure 8. figure 8 . KSZ8895MLub eeprom c onfiguration timing diagram to configure the KSZ8895MLub with a pre - configured eeprom use the following steps: 1. at the board level, connect pin 110 on the KSZ8895MLub to the scl pin on the eeprom. connect pin 111 on the KSZ8895MLub to the sda pin on the eeprom. 2. a[2 - 0] address pins of eeprom should be tied to ground for address a[2 - 0] = 000 to be identified by the KSZ8895MLub . 3. set the input signals ps[1:0] (pins 113 and 114, respectively) to 00. this puts the KSZ8895MLub serial bus configuration into i 2 c master mode. 4. be sure the board - level reset signal is connected to the KSZ8895MLub reset signal on pin 115 (rst_n). 5. program the contents of the eeprom before placing it on the board with the desired configuration data. n ote that the first byte in the eeprom must be 95 for the loading to occur properly. if this value is not correct, all other data will be ignored. 6. place eeprom on the board and power up the board. assert the active - low board level reset to rst_n on the KSZ8895MLub . after the reset is de - asserted, the KSZ8895MLub will begin reading configuration data from the eeprom. the configuration access time (t prgm ) is less than 30ms. note: for proper operation, make sure that pin 47 (pwrdn_n) is not asserted during the reset operati on. spi slave serial bus configuration the KSZ8895MLub can also act as a spi slave device. through the spi, the entire feature set can be enabled, including vlan, igmp snooping, mib counters, etc. the external master device can access any reg ister from register 0 to register 255 randomly. the system should configure all the desired settings before enabling the swit ch in the KSZ8895MLub . to enable the switch, write a "1" to register 1 bit 0. two standard spi commands are supported (00000011 for read data, and 00000010 for write data). to speed configuration time, the KSZ8895MLub also supports multiple reads or writes. after a byte is written to or read from the KSZ8895MLu b , the internal address counter automatically increments if the spi slave select s ignal (spis_n) continues to be driven low. if spis_n is kept low after the first byte is read, the next byte at the next address will be shifted out o n spiq. if spis_n is kep t low after the first byte is written, bits on the master out slave input (spid) line will be written to the next address. asserting spis_n high terminates a read or write operati on. this means that the spis_n signal must be asserted high and then low again before issuing another command and address. the addr ess counter wraps back to zero once it reaches the highest address. therefore the entire register set can be written to or read from by issuing a single command and address. the default spi clock speed is 12.5mhz. the KSZ8895MLub is able to support a spi bus up to 25mhz (set register 12 bit[5:4] = 0x10) . a high performance spi master is recommended to prevent internal counter overflow. april 1, 2014 46 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub to use the KSZ8895MLub spi: 1. at the board level, connect KSZ8895MLu b pins as follows: table 8 . spi connections KSZ8895MLub pin number KSZ8895MLub signal name microprocessor signal description 112 spis_n spi slave select 110 spic spi clock 111 spid master out slave input 109 spiq master in slave output 2. set the input signals ps[1:0] (pins 113 and 114, respectively) to 10 to set the seri al configuration to spi slave mode. 3. power up the board and assert a reset signal. after reset wait 100s, the start switch bit in register 1 will be set to 0. configure the desired settings in the KSZ8895MLub before setting the start register to 1.' 4. write configuration to registers using a typical spi write data cycle as show n in figure 9 or spi multiple write as shown in figure 11. note that data input on spid is registered on the rising edge of spic. 5. registers can be read and configuration can be verified with a typical spi read data cycle as shown in fi gure 10 or a multiple read as shown in figure 12. note that read data is registered out of spiq on the fall ing edge of spic. 6. after configuration is written and verified, write a 1 to register 1 bit 0 to beg in KSZ8895MLub switch operation. spiq spic spid spis_n 0 0 0 0 0 0 1 0 x a7 a6 a5 a4 a3 a2 a1 a0 write command write address write d at a d2 d0 d1 d3 d4 d5 d6 d7 figure 9 . spi write data cycle spiq spic spid spis_n 0 0 0 0 0 0 1 1 x a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 read command read address read d at a figure 10 . spi read data cycle april 1, 2014 47 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub spiq spic spid spis_n 0 0 0 0 0 0 1 0 x a7 a6 a5 a4 a3 a2 a1 a0 write command write address byte 1 d2 d0 d1 d3 d4 d5 d6 d7 spiq spic spid spis_n d7 d6 d5 d4 d4 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 byte 2 byte 3 ... byte n d2 d0 d1 d3 d4 d5 d6 d7 figure 11 . spi multiple write spiq spic spid spis_n 0 0 0 0 0 0 1 1 x a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 read command read address byte 1 x x x x x x x x x x x x x x x x byte 2 byte 3 ... byte n x x x x x x x x x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 spiq spic spid spis_n figure 12 . spi multiple read april 1, 2014 48 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub mii management interface (miim) the KSZ8895MLub supports the standard ieee 802.3 mii management interface, also known as the management data input/output (mdio) interface. this interface allows upper - layer devices to monitor and control the states of the KSZ8895MLub . an external device with mdc/mdio capability is used to read the phy status or configure the p hy settin gs. further details on the miim interface are found in clause 22.2.4.5 of the ieee 802.3u specifi cation. the miim interface consists of the following: ? a physical connection that incorporates the data line (pin 108 mdio) and the clock line (pin 1 07 mdc). ? a specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8895MLub device. ? access to a set of eight 16 - bit registers, consisting of 8 standard miim registers [0:5h], 1d and 1f miim r egisters per port. the miim interface can operate up to a maximum clock speed of 10 mhz mdc clock. table 9 depicts the mii management interface frame format. table 9 . mii management interface frame format preamble start of frame read/write op code phy address bits[4:0] reg address bits[4:0] ta data bits[15:0] idle read 32 1s 01 10 aaaaa rrrrr z0 dddddddd_dddddddd z write 32 1s 01 01 aaaaa rrrrr 10 dddddddd_dddddddd z the miim interface does not have access to all the configuration registers in the KSZ8895MLub . it can only access the standard miim registers. see miim registers. the spi interface and mdc/mdio smi mode, on the other hand, can be used to access all registers with the entire KSZ8895MLub feature set. serial management interface (smi) the smi is the KSZ8895MLub non - standard miim interface that provides access to all KSZ8895MLub configuration registers. this interface allows an external device with mdc/mdio interface to completely monitor and control the state s of the KSZ8895MLub . the smi interface consists of the following: ? a physical connection that incorporates the data line (mdio) and the clock line (mdc). ? a specific protocol that operates across the aforementioned physical connect ion that allows an external controller to communicate with the KSZ8895MLub device. ? access to all KSZ8895MLub configuration registers. register access includes the global, port and advanced c ontrol registers 0 - 255 (0x00 C 0xff), and indirect access to the standard miim registers [0:5] and cust om miim registers [29, 31]. the smi interface can operate up to a maximum clock speed of 1 0 mhz mdc clock. the following table depicts the smi frame format. table 10 . serial management interface (smi) frame format pream ble start of frame read/write op code phy address bits[4:0] reg address bits[4:0] ta data bits [15:0] idle read 32 1s 01 10 rr11r rrrrr z0 0000_0000_dddd_dddd z write 32 1s 01 01 rr11r rrrrr 10 xxxx_xxxx_dddd_dddd z april 1, 2014 49 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub smi register read access is selected when op code is set to 10 and bit s [2:1] of the phy address is set to 11. the 8- bit register address is the concatenation of {phy address bit s [4:3], phy address bit s [0], reg address bit [4:0]}. ta is turn - around bits. ta bits [1:0] are z0 means the processor mdio pin is changed to input hi - z from output mode and the followed 0 is the read response from device , as the switch configuration registers are 8 - bit wide, only the lower 8 bits of data bits [15:0] are used smi register write access is selected when op code is set to 01 and bit s [2:1] of the phy address is set to 11. the 8- bit register address is the concatenation of {phy address bit s [4:3], phy address bit s [0], reg address bit [4:0]}. ta bits [1:0] are set to 1 0 , as the switch configuration registers are 8 - bit wide, only the lower 8 bits of data bits [15:0] are used . to access the KSZ8895MLub registers 0 - 255 (0x00 - 0xff), the following applies: phyad [4, 3, 0] and regad [4:0] are concatenated to form the 8 - bit address; that i s, {phyad [ 4, 3, 0], regad [4:0]} = bits [7:0] of the 8 - bit address. registers are 8 data bits wide. for read operation, data bits [15:8] are read back as zeroes. for wri te operation, data bits [15:8] are not defined, and hence can be set to either zeroes or ones. smi register access is the same as the miim register access, except for the register access requirements presented in this section. april 1, 2014 50 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub register description offset description decimal hex 0 ? 1 0x00 - 0x01 chip id registers 2 ? 13 0x02 - 0x0d glo bal control registers 14 ? 15 0x0e - 0x0f power down management control registers 16 ? 20 0x10 - 0x14 port 1 control registers 21 ? 23 0x15 - 0x17 port 1 reserved (factory test registers) 24 ? 31 0x18 - 0x1f port 1 control/status registers 32 ? 36 0x20 - 0x2 4 port 2 control registers 37 ? 39 0x25 - 0x27 port 2 reserved (factory test registers) 40 ? 47 0x28 - 0x2f port 2 control/status registers 48 ? 52 0x30 - 0x34 port 3 control registers 53 ? 55 0x35 - 0x37 port 3 reserved (factory test registers) 56 ? 63 0x38 - 0x3f port 3 control/status registers 64 ? 68 0x40 - 0x44 port 4 control registers 69 ? 71 0x45 - 0x47 port 4 reserved (factory test registers) 72 ? 79 0x48 - 0x4f port 4 control/status registers 80 ? 84 0x50 - 0x54 port 5 control registers 85 ? 87 0x55 - 0x57 port 5 reserved (factory test registers) 88 ? 95 0x58 - 0x5f port 5 control/status registers 96 ? 103 0x60 - 0x67 reserved (factory testing registers) 104 ? 109 0x68 - 0x6d mac address registers 110 ? 111 0x6e - 0x6f indirect access control registers 112 ? 120 0x70 - 0x78 indirect data registers 121 ? 123 0x79 - 0x7b reserved (factory testing registers) 124 ? 125 0x7c - 0x7d port interrupt registers 126 ? 127 0x7e - 0x7f reserved (factory testing registers) 128 ? 135 0x80 - 0x87 global control registers 136 0x88 switch self test control register 137 ? 143 0x89 - 0x8f qm global control registers 144 ? 145 0x90 - 0x91 tos priority control registers 146 ? 159 0x92 - 0x9f tos priority control registers 160 ? 175 0xa0 - 0xaf reserved (factory testing registers) 176 ? 190 0xb0 - 0xbe port 1 control registers april 1, 2014 51 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub register description (continued) offset description decimal hex 191 0xbf reserved (factory testing register): transmit queue remap base register 192 ? 206 0xc0 - 0xce port 2 control registers 207 0xcf re served (factory testing register) 208 ? 222 0xd0 - 0xde port 3 control registers 223 0xdf reserved (factory testing register) 224 ? 238 0xe0 - 0xee port 4 control registers 239 0xef reserved (factory testing register) 240 ? 254 0xf0 - 0xfe port 5 control r egisters 255 0xff reserved (factory testing register) april 1, 2014 52 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub global registers register 0 (0 00): chip id0 address name description mode default 7 ? 0 f amily id chip family. ro 0 95 register 1 (0 01): chip id1 / start switch address name descripti on mode default 7 ? 4 chip id ro 0 4 3 ? 1 revision id revision id ro 0 0 0 start switch 1, start the chip when external pins (ps1, ps0) = (01) or (1,0) note : in (ps1, p s0) = (0,0) mode, the chip will start automatically, af ter trying to read the external eeprom. if eeprom does not exist, the chip will use default values for all internal registers. if eeprom is present, the contents in the eeprom will be checked. the switch will check: register 0 = 0 95 register 1 [7:4] chip id = 00 if this check is ok, the contents in the eeprom will override chip register default values . c hip will not start when external pins (ps1, ps0) = (1, 0) or (0, 1). note : (ps1, ps0) = (1, 1) for factory test only. 0, stop the switch function of the chip . r/w 0 r egister 2 (0 02): global control 0 address name description mode default 7 new back - off enable new b ack - off algorithm designed for unh 1 = enable 0 = disable r/w 0 6 reserved reserved. ro 0 5 flush dynamic mac table flush the entire dynamic mac tab le for rstp 1 = trigger the flu sh dynamic mac table operation. this bit is self - clear . 0 = n ormal operation note : all the entries associated with a port that has its learning capability being turned off (learning disable) will be flushed. if you want to f lush the entire table, all ports learning capability must be turned off . r/w (sc) 0 april 1, 2014 53 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub global registers (continued) register 2 (0 02): global control 0 address name description mode default 4 flush static mac table flush the matched ent ri es in static m ac table for rstp 1 = trigger the flush static mac table operation. this bit is s elf -c lear (sc) 0 = n ormal operation note : the ma t ched entry is defined as the entry whose forwarding ports field contains a single port and mac address with unicast. this por t, in turn, has its learning capability being turned off (learning disable). per port, multiple entries can be qualified as matched entries. r/w (sc) 0 3 reserved n/a, don t change ro 1 2 reserved n/a, dont change ro 1 1 unh mode 1, the switch will d rop packets with 0x8808 in t/l filed, or da = 01 - 80 - c2 - 00 - 00 - 01. 0, the switch will drop packets qualified as flow control packets. r/w 0 0 link change age 1, link change from link to no link will cause fast aging ( < 800s) to age address table fa ster. after an age cycle is complete, the age logic will return to normal (300 75 seconds ). note: if any port is unplugged, all addresses will be automatically aged out. r/w 0 register 3 (0 03): global control 1 address name description mode defaul t 7 pass all frames 1, switch all packets including bad ones. used solely for debugging purpose. works in conjunction with sniffer mode. r/w 0 6 2k byte packet support 1 = e nable support 2k byte packet 0 = d isable support 2k byte packet r/w 0 5 ieee 8 02.3x transmit flow control disable 0, will enable transmit flow control based on an result. 1, will not enable transmit flow control regardless of an result. r/w 0 pin pmrxd3 strap option. pd(0): enable tx flow control (default). pu(1): disable tx/rx flow control. note : spflc has internal pull - down. april 1, 2014 54 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub global registers (continued) register 3 (0 03): global control 1 address name description mode default 4 ieee 802.3x receive flow control disable 0, will enable receive flow control based on an re sult. 1, will not enable receive flow control regardless of an result. note : bit 5 and bit 4 d efault values are controlled by the same pin, but they can be programmed independently. r/w 0 pin pmrxd3 strap option. pd (0): enable rx flow control (defaul t). pu(1): disable tx/rx flow control. note : spflc has internal pull - down. 3 frame length field check 1, will check frame length field in the ieee packets. if the actual length does not match, the packet will be dropped (for l/t <1500). r/w 0 2 aging enable 1, e nable age function in the chip. 0, d isable aging function. r/w 1 pin led[5][2] strap option. pd(0): aging disable. pu(1): aging enable (default). note : led[5][2] has internal pull up. 1 fast age enable 1 = turn on fast age (800s). r/w 0 0 aggressive back off enable 1 = enable more aggressive back - off algorithm in half duplex mode to enhance performance. this is not an ieee standard. r/w 0 pin pmrxd0 strap option. pd(0): disable aggressive back off (default). pu(1): aggressive back off. note : sppe has internal pull down. april 1, 2014 55 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub global registers (continued) register 4 (0 04): global control 2 address name description mode default 7 unicast port - vlan mismatch discard this feature is used for port vlan (described i n register 17, register 33...). 1, all packets can not cross vlan boundary. 0, unicast packets (excluding unknown/ multicast/broadcast) can cross vlan boundary. r/w 1 6 multicast storm protection disable 1, broadcast storm protection does not include multicast packets. only da=ffffffffffff packets will be regulated. 0, broadcast storm protection includes da = ffffffffffff and da[40] = 1 packets. r/w 1 5 back pressure mode 1, carrier sense based backpressure is selected. 0, collision based backpressure is selected. r/w 1 4 flow control and back pressure fair mode 1, fair mode is selected. in this mode, if a flow control port and a non - flow control port talk to the same destination port, packets from the non - flow control port may be dropped. this is to prevent the flow control port from being flow controlled for an extended period of time. 0, in this mode, if a flow control port and a non - flow control port talk to the same destination port, the flow control port will be flow controlled. this may not be fair to the flow control port. r/w 1 3 no excessive c ollision drop 1, the switch will not drop packets when 16 or more collisions occur. 0, the switch will drop packets when 16 or more collisions occur. r/w 0 pin pmrxd1 strap option. pd(0): (default ) drop excess ive collision packets. pu(1): dont drop excessive collision packets. note : spdecp has internal pull down. 2 huge packet support 1, will accept packet sizes up to 1916 bytes (inclusive). this bit setting will override setting from bit 1 of the same regis ter. 0, the maximum packet size will be determined by bit 1 of this register. r/w 0 april 1, 2014 56 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub global registers (continued) register 4 (0 04): global control 2 address name description mode default 1 legal maximum packet size check disable 1, will accept packet sizes up to 1536 bytes (inclusive). 0, 1522 bytes for tagged packets (not including packets with stpid from cpu to ports 1 - 4), 1518 bytes for untagged packets. any packets larger than the specified value will be dropped. r/w 0 pin pmrxer strap op tion. pd(0): (default) 1518/1522 byte packets. pu(1): 1536 byte packets. note : sppsz has internal pull - down. 0 reserved n/a ro 0 register 5 (0 05): global control 3 address name description mode default 7 802.1q vlan enable 1, 802.1q vlan mode is turned on. vlan table needs to set up before the operation. 0, 802.1q vlan is disabled. r/w 0 6 igmp snoop enable on switch sw5 - mii interface 1, igmp snoop enabled. all the igmp packets will be forwarded to switch mii port. 0, igmp snoop disabled. r/w 0 5 enable direct mode on switch sw5 - mii interface 1, direct mode on port 5. this is a special mode for the switch mii interface. using preamble before mrxdv to direct switch to forward packets, bypassing internal look - up. 0, normal operation. r/ w 0 4 enable pre - tag on switch sw5 - mii interface 1, packets forwarded to switch mii interface will be pre - tagged with the source port number (preamble before mrxdv). 0, normal operation. r/w 0 3 ? 2 reserved n/a ro 00 1 enable tag mask 1, the las t 5 digits in the vid field are used as a mask to determine which port(s) the packet should be forwarded to. 0, no tag masks. note : t urn off the 802.1q vlan mode (reg0x5, bit 7 = 0) for this bit to work. r/w 0 0 sniff mode select 1, will do rx and tx sniff (both source port and destination port need to match). 0, will do rx or tx sniff (either source port or destination port needs to match). this is the mode used to implement rx only sniff. r/w 0 april 1, 2014 57 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub global registers (continued) register 6 (0 06 ): global control 4 address name description mode default 7 switch sw5 - mii back p ressure enable 1, enable half - duplex back pressure on switch mii interface. 0, disable back pressure on switch mii interface. r/w 0 6 switch sw5 - mii half - duplex mode 1, enable mii interface half - duplex mode. 0, enable mii interface full - duplex mode. r/w pin smrxd2 strap option. pd(0): (default) full - duplex mode. pu(1): half - duplex mode. note : smrxd2 has internal pull - down. 5 switch sw5 - mii flow control enable 1, enabl e full - duplex flow control on switch mii interface. 0, disable full - duplex flow control on switch mii interface. r/w pin smrxd3 strap option. pd(0): (default) disable flow control. pu(1): enable flow control. note : smrxd3 has internal pull - down. 4 swi tch sw5 - mii speed 1, the switch sw5 - mii is in 10mbps mode. 0, the switch sw5 - mii is in 100mbps mode . r/w pin smrxd1 strap option. pd(0): (default) enable 100mbps. pu(1): enable 10mbps. note : smrxd1 has internal pull - down. 3 null vid replacement 1, wil l replace null vid with port vid (12 bits). 0, no replacement for null vid. r/w 0 2 ? 0 broadcast storm protection rate bit [10:8] this along with the next register determines how many 64 byte blocks of packet data allowed on an input port in a preset period. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. r/w 000 april 1, 2014 58 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub global registers (continued) register 7 (0 07): global control 5 address name description mode default 7 ? 0 broadcast storm protection rate bit [7:0] this along with the previous register determines how many 64 byte blocks of packet data are allowed on an input port in a preset period. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. r/w 0x4a (1) note : 1. 148,800 frames/sec 1% = 74 frames/i nterval (approx.) = 0 4a. register 8 (0 08): global control 6 address name description mode default 7 ? 0 factory testing reserved r/w 0 24 register 9 (0 09): global control 7 address name description mode default 7 ? 0 factory testing reser ved r/w 0 28 register 10 (0 0a): global control 8 address name description mode default 7 ? 0 factory testing reserved r/w 0 00 register 11 (0 0b): global control 9 address name description mode default 7 reversed n/a, dont change ro 0 6 reserved n/a, dont change ro 0 5 reserved n/a, dont change ro 0 4 reserved n/a, dont change ro 0 3 phy power save 1 = disable phy power - save mode. 0 = enable phy power - save mode. r/w 0 2 reserved n/a, dont change ro 0 april 1, 2014 59 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub global registers (continued) register 11 (0 0b): global control 9 address name description mode default 1 led mode 0 = led mode 0. 1 = led mode 1. mode 0, link at 100/full ledx[2,1,0]=0,0,0 100/half ledx[2,1,0]=0,1,0 10/full ledx[2,1,0]=0,0,1 10/half ledx[2,1,0]=0, 1,1 mode 1, link at 100/full ledx[2,1,0]=0,1,0 100/half ledx[2,1,0]=0,1,1 10/full ledx[2,1,0]=1,0,0 10/half ledx[2,1,0]=1,0,1 (0=led on, 1=led off) r/w pin smrxd0 - strap option. pull - down(0): enabled led mode 0. pull - up(1): enabled led mode 1. note : smrxd0 has internal pull - down 0. mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act ledx_0 speed fulld 0 spi /smi read sampling clock edge select select the spi /smi clock edge for sampling spi /smi read data 1 = trigger by rising edge of spi /smi clock ( for high speed spi about 25mhz and smi about 10mhz ) 0 = trigger by falling edge of spi /smi clock r/w 0 april 1, 2014 60 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub global registers (continued) register 12 (0 0c): global control 10 address name description mode defau lt 7 reserved n/a, don t change ro 0 6 reserved n/a, dont change ro 1 5 ? 4 cpu interface clock select select the internal clock speed for spi, mdi interface: 00 = 41.67mhz (spi up to 6.25mhz, mdc up to 6mhz) 01 = 83.33mhz default (spi scl up to 12.5mh z, mdc up to 12mhz) 10 = 125mhz (for high - speed spi about 25mhz) 11 = reserved r/w 01 3 reserved n/a ro 00 2 reserved n/a, don t change ro 1 1 tail tag enable tail tag feature is applied for port 5 only. 1 = insert 1 byte of data right before fcs 0 = do not insert r/w 0 0 pass flow control packet 1 = switch will not filter 802.1x flow control packets 0 = switch will filter 802.1x flow control packets r/w 0 register 13 (0 0d): global control 11 address name description mode default 7 ? 0 fact ory testing n/a, dont change ro 00000000 april 1, 2014 61 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub global registers (continued) register 14 (0 0e): power - down management control 1 address name description mode default 7 reserved n/a, don t change ro 0 6 reserved n/a, don t change ro 0 5 pll power down pll power down: 1 = disable 0 = enable note : i t takes the effect in the energy detect mode (edpd mode) . r/w 0 4 ? 3 power management mode power management mode: 00 = normal mode (d0) 01 = energy detection mode (d2) 10 = soft power down mode (d3) 11 = power saving mode (d1) r/w 00 pin led[ 4 ][ 0 ] strap option. pd(0): select energy detection mode pu(1): (default) normal mode note : led[ 4 ][ 0 ] has internal pull - up. register 14 (0 0e): power - down management control 1 address name description mode default 2 ? 1 reserved n/a, don t change r/w 00 0 reserved n/a, dont change ro 0 register 15 (0 0f): power - down management control 2 address name description mode default 7 - 0 go_sleep_time[7:0] when the energy detect mode is on, this value is used to co ntrol the minimum period that the no energy event has to be detected consecutively before the device enters the low power state. the unit is 20 ms. the default of go_sleep time is 1.6 seconds (80dec x 20ms) . r/w 01010000 april 1, 2014 62 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port registers the following registers are used to enable features that are assigned on a per port basis. the register bi t assignments are the same for all ports, but the address for each port is different, as indicated: register 16 (0 10): port 1 control 0 register 32 (0 20): port 2 control 0 register 48 (0 30): port 3 control 0 register 64 (0 40): port 4 control 0 register 80 (0 50): port 5 control 0 address name description mode default 7 broadcast storm protection enable 1, enable broadcast storm protection for ingress packets on the port. 0, disable broadcast storm protection. r/w 0 6 diffserv priority classification enable 1, enable diffserv priority classification for ingress packets on port. 0, disable diffserv function. r/w 0 5 802.1p priority classification enable 1, enable 802.1p priority classification for ingress packets on port. 0, disable 802.1p. r/w 0 4 ? 3 port- based priority classification enable = 00, ingress packets on port will be classified as priority 0 queue if diffserv or 802.1p classification is not enabled or fails to classify. = 01, ingress packets on port will be classified as priority 1 queue if diffserv or 802.1p classification is not enabled or fails to classify. = 10, ingress packets on port will be classified as priority 2 queue if diffserv or 802.1p classification is not enabled or fails to classify. = 11, ingress packets on port will be classified as priority 3 queue if diffserv or 802.1p classification is not enabled or fails to classify. note : diffserv, 802.1p and po rt priority can be en abled at the same time. the or d result of 802.1p and dscp overwrites the port priority. r/w 00 2 tag insertion 1, when packets are output on the port, the switch will add 802.1q tags to packets without 802.1q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress ports port vid. 0, disable tag insertion. r/w 0 1 tag removal 1, when packets are output on the port, the switch will remove 802.1q tags from packets with 802.1q t ags when received. the switch will not modify packets received without tags. 0, disable tag removal. r/w 0 april 1, 2014 63 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port registers (continued) register 16 (0 10): port 1 control 0 register 32 (0 20): port 2 control 0 register 48 (0 30): port 3 control 0 regist er 64 (0 40): port 4 control 0 register 80 (0 50): port 5 control 0 address name description mode default 0 two queues split enable this bit0 in the register16 /32/48/64/80 should be combination with register177/193/209/225/241 bit 1 for port 1 - 5 will select the split of 1/2/4 queues: for port 1, [register177 bit 1, register16 bit 0] = [11], reserved [1 0 ], the port output queue is split into four priority queues or if map 802.1p to priority 0 - 3 mode. [01], the port output queue is split into two priori ty queues or if map 802.1p to priority 0 - 3 mode . [00], single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority. r/w 0 register 17 (0 11): port 1 control 1 register 33 (0 21): port 2 control 1 register 49 (0 31): port 3 control 1 register 65 (0 41): port 4 control 1 register 81 (0 51): port 4 control 1 address name description mode default 7 sniffer port 1, port is designated as sniffer port and will transmit packets that are monitored. 0, port is a normal port. r/w 0 6 receive sniff 1, all the packets received on the port will be marked as monitored packets and forwarded to the designated sniffer port. 0, no receive monitoring. r/w 0 5 transmit sniff 1, all the packets transmitted on the port will be marked as monitored packets and forwarded to the designated sniffer port. 0, no transmit monitoring. r/w 0 4 ? 0 port vlan membership define the ports port vlan membership. bit 4 stands for port 5, bit 3 for port 4...bit 0 for port 1. the port can only communicate within the membership. a 1 includes a port in the membership; a 0 excludes a port from membership. r/w 0x1f april 1, 2014 64 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port registers (continued) register 18 (0 12): port 1 control 2 register 34 (0 22): port 2 control 2 register 50 (0 32): port 3 control 2 register 66 (0 42): port 4 control 2 register 82 (0 52): port 5 control 2 address name description mode default 7 user priority ceiling 1, if packet s user priority field is greater than the user priority field in the port default tag register, replace the packets user priority field with the user priority field in the port default tag register control 3. 0, no replace packet s priority filed with port default tag priority filed of the port register control 3 bit [7:5]. r/w 0 6 ingress vlan filtering. 1, the switch will discard packets whose vid port membership in vlan table bit s [ 11 :7 ] does not include the ingress port. 0, no ingress vlan filtering. r/w 0 5 discard non - pvid packets 1, th e switch will discard packets whose vid does not match ingress port default vid. 0, no packets will be discarded. r/w 0 april 1, 2014 65 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port registers (continued) register 18 (0 12): port 1 control 2 register 34 (0 22): port 2 control 2 register 50 (0 32): port 3 control 2 register 66 (0 42): port 4 control 2 register 82 (0 52): port 5 control 2 address name description mode default 4 force flow control 1, will always enable rx and tx flow control on the port, regardless of an result. 0, the flow control is enabl ed based on an result (default) note: this bit is reserved for port 5, sw5 - mii use the register 6 bit5 for the flow control. r/w 0 strap- in option led1_1/pcol for port 3/port 4 led1_1 default pull up (1): not force flow control; pcol default pull - down (0): not force flow control. led1_1 pull down (0): force flow control; pcol pull - up (1): force flow control. note : led1_1 has internal pull - up; pcol have internal pull - down . 3 back pressure enable 1, enable port half - duplex back pressure. 0, disable por t half - duplex back pressure. note: this bit is reserved for port 5, sw5 - mii use the register 6 bit 7 for the back pressure. r/w 0 pin pmrxd2 strap option. pull- down (0): disable back pressure. pull- up(1): enable back pressure. note : pmrxd2 has internal pull - down. 2 transmit enable 1, enable packet transmission on the port. 0, disable packet transmission on the port. r/w 1 1 receive enable 1, enable packet reception on the port. 0, disable packet reception on the port. r/w 1 0 learning disable 1, disable switch address learning capability. 0, enable switch address learning. r/w 0 april 1, 2014 66 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port registers (continued) register 19 (0 13): port 1 control 3 register 35 (0 23): port 2 control 3 register 51 (0 33): port 3 control 3 register 67 (0 43): port 4 control 3 register 83 (0 53): port 5 control 3 address name description mode default 7 ? 0 default tag [15:8] ports default tag, containing: 7 ? 5: user priority bits 4: cfi bit 3 ? 0 : vid[11:8] r/w 0 register 20 (0 14): port 1 control 4 reg ister 36 (0 24): port 2 control 4 register 52 (0 34): port 3 control 4 register 68 (0 44): port 4 control 4 register 84 (0 54): port 5 control 4 address name description mode default 7 ? 0 default tag [7:0] default port 1s tag, containing: 7 ? 0: vid [7:0] r/w 1 note: registers 19 and 20 (and those corresponding to other ports) serve two purposes: (1) associated with the ingress untagged packets, and used for egress tagging; (2) default vid for the ingress untagged or null - vid - tagged packets, and used for address look up. register 87 (0 57): reserved control register address name description mode default 7 ? 0 reserved n/a, don t change ro 0 00 april 1, 2014 67 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port registers (continued) register 25 (0 19): port 1 status 0 register 41 (0 29): port 2 status 0 register 57 (0 39): port 3 status 0 register 73 (0 49): port 4 status 0 register 89 (0 59): reserved address name description mode default 7 hp_mdix 1 = hp auto mdi/mdi - x mode 0 = micrel auto mdi/mdi - x mode r/w 1 6 factory testing reserved ro 0 5 p olrvs 1 = polarity is reversed 0 = polarity is not reversed ro 0 4 transmit flow control enable 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive ro 0 3 receive flow control enable 1 = receive flow control feature is active 0 = receive flow control feature is inactive ro 0 2 operation speed 1 = link speed is 100mbps 0 = link speed is 10mbps ro 0 1 operation duplex 1 = link duplex is full 0 = link duplex is half ro 0 0 reserved n/a ro 0 register 26 (0 1a): port 1 phy special control/status register 42 (0 2a): port 2 phy special control/status register 58 (0 3a): port 3 phy special control/status register 74 (0 4a): port 4 phy special control/status register 90 (0 5a): reserved address name description mode defa ult 7 vct 10m short 1 = less than 10 meter short detected ro 0 6 - 5 vct_result 00 = normal condition 01 = open condition detected in cable 10 = short condition detected in cable 11 = cable diagnostic test has failed ro 00 4 vct_enable 1 = enable cable diagnostic test. after vct test has completed, this bit will be self - cleared. 0 = indicate cable diagnostic test (if enabled) has completed and the status information is valid for read. r/w (sc) 0 3 force_lnk 1 = force link pass 0 = normal operation r/w 0 2 pwrsave 1 = enable power saving 0 = disable power saving r/w 0 1 remote loopback 1 = perform remote loopback, loopback on port 1 as follows: port 1 (reg. 26, bit 1 = 1) start : rxp1/rxm1 (port 1) loopback: pmd/pma of port 1 s phy end: txp1/txm1 (port 1) setting reg. 42, 58, 74, 90, bit 1 = 1 will perform remote loopback on port 2, 3, 4, 5. 0 = normal operation. r/w 0 0 vct_fault_count [8] bits[8 ] of vct fault count . ro 0 april 1, 2014 68 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port registers (continued) reg ister 27 (0 1b): port 1 linkmd result register 43 (0 2b): port 2 linkmd result register 59 (0 3b): port 3 linkmd result register 75 (0 4b): port 4 linkmd result register 91 (0 5b): reserved address name description mode default 7-0 vct_fault_count [7:0] bits[7:0] of vct fault count distance to the fault. its approximately 0.4m*vct_fault_count [8:0] ro 0 register 28 (0 1c): port 1 control 5 register 44 (0 2c): port 2 control 5 register 60 (0 3c): port 3 control 5 register 76 (0 4c): port 4 control 5 re gister 92 (0 5c): reserved address name description mode default 7 disable auto - negotiation 1, disable auto - negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 0, auto - negotiation is on. note: the register bit value is the invert of the strap value at the pin. r/w 0 for port 3/port 4 only. invert of pins led[2][1]/led[5][0] strap option. pd(0): disable auto - negotiation. pu(1): enable auto - negotiation. note : led[2][1]/led[5][0] have internal pull up. 6 forced speed 1, forc ed 100bt if an is disabled (bit 7). 0, forced 10bt if an is disabled (bit 7). r/w 1 5 forced duplex 1, forced full - duplex if (1) an is disabled or (2) an is enabled but failed. 0, forced half - duplex if (1) an is disabled or (2) an is enabled but failed (default). r/w 0 for port 3/port 4 only. pins led1_0/pcrs strap option. 1. for force half - duplex: led1_0 pin pull - up(1) (default) pcrs pin pull - down (0) (default). 2. for f orce full - duplex : led1_0 pin pull- down (0). pcrs pull - up (1): note : led1_0 has in ternal pull - up; pcrs have internal pull down . april 1, 2014 69 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port registers (continued) register 28 (0 1c): port 1 control 5 register 44 (0 2c): port 2 control 5 register 60 (0 3c): port 3 control 5 register 76 (0 4c): port 4 control 5 register 92 (0 5c): reserved add ress name description mode default 4 advertised flow control capability 1, advertise flow control capability. 0, suppress flow control capability from transmission to link partner. r/w 1 3 advertised 100bt full - duplex capability 1, advertise 100bt full - duplex capability. 0, suppress 100bt full - duplex capability from transmission to link partner. r/w 1 2 advertised 100bt half - duplex capability 1, advertise 100bt half - duplex capability. 0, suppress 100bt half - duplex capability from transmission t o link partner. r/w 1 1 advertised 10bt full - duplex capability 1, advertise 10bt full - duplex capability. 0, suppress 10bt full - duplex capability from transmission to link partner. r/w 1 0 advertised 10bt half - duplex capability 1, advertise 10bt half - duplex capability. 0, suppress 10bt half - duplex capability from transmission to link partner. r/w 1 register 29 (0 1d): port 1 control 6 register 45 (0 2d): port 2 control 6 register 61 (0 3d): port 3 control 6 register 77 (0 4d): port 4 control 6 reg ister 93 (0 5d): reserved address name description mode default 7 led off 1, turn off all ports leds (ledx_2, ledx_1, ledx_0, where x is the port number). these pins will be driven high if this bit is set to one. 0, normal operation. r/w 0 6 txi ds 1, disable ports transmitter. 0, normal operation. r/w 0 5 restart an 1, restart auto - negotiation. 0, normal operation. r/w (sc) 0 4 fx reserved n/a ro 0 3 power down 1, power down. 0, normal operation. r/w 0 2 disable auto mdi/mdi - x 1, disable auto mdi/mdi - x function. 0, enable auto mdi/mdi - x function. r/w 0 1 forced mdi 1, if auto mdi/mdi - x is disabled, force phy into mdi mode. 0, mdi -x mode. r/w 0 april 1, 2014 70 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port registers (continued) register 29 (0 1d): port 1 control 6 register 45 (0 2 d): port 2 control 6 register 61 (0 3d): port 3 control 6 register 77 (0 4d): port 4 control 6 register 93 (0 5d): reserved address name description mode default 0 mac loopback 1 = perform mac loopback, loop back path as follows: e.g. set port 1 mac loopback (reg. 29, bit 0 = 1), use port 2 as monitor port. the packets will transfer start: port 2 receiving (also can start to receive packets from port 3, 4, 5). loop - back: port 1s mac. end: port 2 transmitting (also can end at port 3, 4, 5 respectively). setting reg. 45, 61, 77, 93, bit 0 = 1 will perform mac loopback on port 2, 3, 4, 5 respectively. 0 = normal operation. r/w 0 register 30 (0 1e): port 1 status 1 register 46 (0 2e): port 2 status 1 register 62 (0 3e): port 3 stat us 1 register 78 (0 4e): port 4 status 1 register 94 (0 5e): reserved address name description mode default 7 mdix status 1, mdi . 0, mdi -x . ro 0 6 an done 1, an done. 0, an not done. ro 0 5 link good 1, link good. 0, link not good. ro 0 4 pa rtner flow control capability 1, link partner flow control capable. 0, link partner not flow control capable. ro 0 3 partner 100bt full - duplex capability 1, link partner 100bt full - duplex capable. 0, link partner not 100bt full - duplex capable. ro 0 2 partner 100bt half - duplex capability 1, link partner 100bt half - duplex capable. 0, link partner not 100bt half - duplex capable. ro 0 1 partner 10bt full - duplex capability 1, link partner 10bt full - duplex capable. 0, link partner not 10bt full - duplex capable. ro 0 0 partner 10bt half - duplex capability 1, link partner 10bt half - duplex capable. 0, link partner not 10bt half - duplex capable. ro 0 april 1, 2014 71 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port registers (continued) register 31 (0 1f): port 1 control 7 and status 2 register 47 (0 2f): port 2 control 7 and status 2 register 63 (0 3f): port 3 control 7 and status 2 register 79 (0 4f): port 4 control 7 and status 2 register 95 (0 5f): reserved address name description mode default 7 phy loopback 1 = perform phy loopback, loop back path as follows: e.g. set port 1 phy loopback (reg. 31, bit 7 = 1) use the port 2 as monitor port. the packets will transfer start: port 2 receiving (also can start from port 3, 4, 5). loopback: pmd/pma of port 1s phy end: port 2 transmitting (also can end at port 3, 4, 5 respectively). setting reg. 47, 63, 79, 95, bit 7 = 1 will perform phy loopback on port 2, 3, 4, 5 respectively. 0 = normal operation. r/w 0 6 reserved ro 0 5 phy isolate 1, electrical isolation of phy from mii and tx+/tx - . 0, normal operation. r/w 0 4 soft reset 1, phy soft reset. this bit is self - clear. 0, normal operation. r/w (sc) 0 3 force link 1, force link in the phy. 0, normal operation r/w 0 2 ? 0 port operation mode indication indica te the current state of port operation mode: [000] = r eserved [001] = still in auto - negotiation [010] = 10base- t half duplex [011] = 100base- tx /fx half duplex [100] = r eserved [101] = 10base- t full duplex [110] = 100base- tx /fx full duplex [111] = reserved ro 001 note : port control 12 and 13, 14 and port status 1, 2 contents can be accessed by miim (mdc/mdio) interface via the standard miim register definition. april 1, 2014 72 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers registers 104 to 109 define the switching engines mac address. this 48 - bit address is used as the source address in mac pause control frames. register 104 (0 68): mac address register 0 address name description mode default 7 ? 0 maca[47:40] r/w 0x00 register 105 (0 69): mac address register 1 address name description mode default 7 ? 0 maca[39:32] r/w 0x10 register 106 (0 6a): mac address register 2 address name description mode default 7 ? 0 maca[31:24] r/w 0xa1 register 107 (0 6b): mac address register 3 address name descriptio n mode default 7 ? 0 maca[23:16] r/w 0xff register 108 (0 6c): mac address register 4 address name description mode default 7 ? 0 maca[15:8] r/w 0xff register 109 (0 6d): mac address register 5 address name description mode defau lt 7 ? 0 maca[7:0] r/w 0xff april 1, 2014 73 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) use registers 110 and 111 to read or write data to the static mac addres s table, vlan table, dynamic address table, or the mib counters. register 110 (0 6e): indirect access control 0 address name description mode default 7 ? 5 reserved reserved. r/w 000 4 read high write low 1, read cycle. 0, write cycle. r/w 0 3 ? 2 table select 00 = static mac address table selected. 01 = vlan table selected. 10 = dynamic address table selected. 11 = mib counter selected. r/w 0 1 ? 0 indirect address high bit 9 ? 8 of indirect address. r/w 00 register 111 (0 6f): indirect access control 1 address name description mode default 7 ? 0 indirect address low bit 7 ? 0 of indirect address. r/w 00000000 note : write to register 111 will actually trigger a command. read or write access will be decided by bi t 4 of register 110. register 112 (0 70): indirect data register 8 address name description mode default 68 ? 64 indirec t data bit 68 ? 64 of indirect data. r/w 00000 register 113 (0 71): indirect data register 7 address name description mode default 63 ? 56 indirect data bit 63 ? 56 of indirect data. r/w 00000000 register 114 (0 72): indirect data register 6 address name description mode default 55 ? 48 indirect data bit 55 ? 48 of indirect data. r/w 00000000 register 115 (0 73): indirect data register 5 address name description mode default 47 ? 40 indirect data bit 47 ? 40 of indirect data. r/w 00000000 register 116 (0 74): indirect data register 4 address name description mode default 39 ? 32 indirect data bit 39 ? 32 of indirect data. r/w 00000000 april 1, 2014 74 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) use registers 110 and 111 to read or write data to the static mac address table, vlan tab le, dynamic address table, or the mib counters. register 117 (0 75): indirect data register 3 address name description mode default 31 ? 24 indirect data bit of 31 ? 24 of indirect data r/w 00000000 register 118 (0 76): indirect data register 2 address name description mode default 23 ? 16 indirect data bit 23 ? 16 of indirect data. r/w 00000000 register 119 (0 77): indirect data register 1 address name des cription mode default 15 ? 8 indirect data bit 15 ? 8 of indirect data. r/w 00000000 register 120 (0 78): indirect data register 0 address name description mode default 7 ? 0 indirect data bit 7 ? 0 of indirect data. r/w 00000000 regis ter 124 (0x7c): interrupt status register address name description mode default 7 ? 5 reserved reserved ro 000 4 reserved reserved ro 0 3 port 4 interrupt status 1, port 4 interrupt request 0, normal note : this bit is set by port 4 link change. write a 1 to clear this bit ro 0 2 port 3 interrupt status 1, port 3 interrupt request 0, normal note : this bit is set by port 3 link change. write a 1 to clear this bit ro 0 1 port 2 interrupt status 1, port 2 interrupt request 0, normal note : this bi t is set by port 2 link change. write a 1 to clear this bit ro 0 0 port 1 interrupt status 1, port 1 interrupt request 0, normal note : this bit is set by port 1 link change. write a 1 to clear this bit ro 0 april 1, 2014 75 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) us e registers 110 and 111 to read or write data to the static mac address table, vlan table, dynamic address table, or the mib counters. register 125 (0x7d): interrupt mask register address name description mode default 7 ? 5 reserved reserved. ro 000 4 reserved reserved ro 0 3 port 4 interrupt mask 1, port 4 interrupt mask 0, normal r/w 0 2 port 3 interrupt mask 1, port 3 interrupt mask 0, normal r/w 0 1 port 2 interrupt mask 1, port 2 interrupt mask 0, normal r/w 0 0 port 1 interrupt mask 1, port 1 interrupt mask 0, normal r/w 0 the registers 128, 129 can be used to map from 802.1p priority field 0- 7 to switchs four priority queues 0-3 , 0x3 is highest priority queues as priority 3, 0x0 is lowest priority queues as priority 0. register 128 (0x8 0): global control 12 address name description mode default 7 - 6 tag_0x3 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x3 r/w 0x1 5 - 4 tag_0x2 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x2 r/w 0x1 3 - 2 tag_0x1 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x1 r/w 0x0 1 - 0 tag_0x0 ie ee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x0 r/w 0x0 register 129 (0x81): global control 13 address name description mode default 7 - 6 tag_0x7 ieee 802.1p mapping. the value i n this field is used as the frames priority when its ieee 802.1p tag has a value of 0x7 r/w 0x3 5 - 4 tag_0x6 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x6 r/w 0x3 3 - 2 tag_0x5 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x5 r/w 0x2 1 - 0 tag_0x4 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a valu e of 0x4 r/w 0x2 april 1, 2014 76 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 130 (0x82): global control 14 address name description mode default 7 ? 6 pri_2q[1: 0] (note that program prio_2q[1:0] = 01 is not supported and should be avoided) when the 2 queue configuration is selected, these pri_2q[1: 0 ] bits are used to map the 2 - bit result of ieee 802.1p from register 128/129 or tos/diffserv from register 144 - 159 mapping (for 4 queues) into two queues low/high priorit ies . 2- bit result of ieee 802.1p or tos/diff serv 00 (0) = map to low priority queue 01 (1) = prio_2q[0] map to low/high priority queue 10 (2) = prio_2q[1] map to low/high priority queue 11 (3) = map to high priority queue pri_2q[1:0] = 00: result 0, 1, 2 are low priority. 3 is high priority. 10: r esult 0, 1 are low priority. 2, 3 are high priority (default). 11: result 0 is low priority. 1, 2, 3 are high priority. r/w 10 5 reserved n/a, dont change ro 0 4 reserved n/a, dont change ro 0 3 ? 2 reserved n/a, dont change ro 01 1 reserved n/a, do nt change ro 0 0 reserved n/a, dont change ro 0. register 131 (0x83): global control 15 address name description mode default 7 reserved n/a ro 1 6 reserved n/a ro 0 5 unknown unicast packet forward 1 = enable supporting unknown unicast packet forward 0 = disable r/w 0 4 ? 0 unknown unicast packet forward port map 00000 = filter unknown unicast packet 00001 = forward unknown unicast packet to port 1 00011 = forward unknown unicast packet to port 1, port 2 11111 = broadcast unknown unicast pac ket to all ports r/w 00000 april 1, 2014 77 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 132 (0x84): global control 16 address name description mode default 7 ? 6 chip i/o output drive strength select[1:0] output drive strength select[1:0] = 00 = 4ma drive streng th 01 = 8ma drive strength (default) 10 = 12ma drive strength 11 = 16 ma drive strength note : bit[1] value is the invert of the strap value at the pin. bit[0] value is the same of the strap value at the pin r/w pin led[3][0] strap option. pull - down (0): se lect 12ma drive strength. pull - up (1): select 8ma drive strength. note : led[3][0] has internal pull - up. 5 unknown multicast packet forward (not including ip multicast packet) 1 = enable supporting unknown multicast packet forward 0 = disable r/w 0 4 ? 0 unknown multicast packet forward port map 00000 = filter unknown multicast packet 00001 = forward unknown multicast packet to port 1 00011 = forward unknown multicast packet to port 1, port 2 11111 = broadcast unknown multicast packet to all ports r/w 00000 register 133(0x85): global control 17 address name description mode default 7 - 6 reserved ro 00 5 unknown vid packet forward 1 = enable supporting unknown vid packet forward 0 = disable r/w 0 4 - 0 unknown vid packet forward port map 00000 = filter unknown vid packet 00001 = forward unknown vid packet to port 1 00011 = forward unknown vid packet to port 1, port 2 11111 = broadcast unknown vid packet to all ports r/w 00000 april 1, 2014 78 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 134 (0x86): global control 18 address name description mode default 7 reserved n/a ro 0 6 self- address filter enable 1 = enable filtering of self - address unicast and multicast packet 0 = do not filter self - address packet note : the self - address filtering will filter pac kets on the egress port, self mac address is assigned in the register 104 ? 109. r/w 0 5 unknown ip multicast packet forward 1 = enable supporting unknown ip multicast packet forward 0 = disable r/w 0 4 ? 0 unknown ip multicast packet forward port map 00 000 = filter unknown ip multicast packet 00001 = forward unknown ip multicast packet to port 1 00011 = forward unknown ip multicast packet to port 1, port 2 11111 = broadcast unknown ip multicast packet to all ports r/w 00000 register 135 (0x87): globa l control 19 address name description mode default 7 reserved n/a, dont change ro 0 6 reserved n/a, dont change ro 0 5 ? 4 ingress rate limit period the unit period for calculating ingress rate limit 00 = 16 ms 01 = 64 ms 1x = 256 ms r/w 01 3 que ue - based egress rate limit enabled enable queue - based egress rate limit 0 = port - base egress rate limit (default) 1 = queue - based egress rate limit r/w 0 2 insertion source port pvid tag selection enable 1 = enable source port pvid tag insertion or non - i nsertion option on the egress port for each source port pvid based on the ports registers control 8. 0 = disable, all packets from any ingress port will be inserted pvid based on port register control 0 bit 2. r/w 0 1 ? 0 reserved n/a, dont change ro 00 april 1, 2014 79 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 144 (0x90): tos priority control register 0 the ipv4/ipv6 tos priority control registers implement a fully decoded 64 bit differentiated s ervices code point (dscp) register used to determine priority from the 6 bit tos field in the ip header. the most significant 6 bits of the tos field are fully decoded int o 64 possibilities, and the singular code that results is mapped to the value in the corresponding bit in the dscp register. address name descriptio n mode default 7 ? 6 dscp[7:6] ipv4 and ipv6 mapping the value in this field is used as the frames priority when bits[7:2] of the frames ip tos/diffserv/traffic class value is 0x0c r/w 00 5 ? 4 dscp[5:4] ipv4 and ipv6 mapping the value in this field is used as the frames priority when bits[7:2] of the frames ip tos/diffserv/traffic class value is 0x08 r/w 00 3 ? 2 dscp[3:2] ipv4 and ipv6 mapping the value in this field is used as the frames priority when bits[7:2] of the frames ip tos/diffserv/ traffic class value is 0x04 r/w 00 1 ? 0 dscp[1:0] ipv4 and ipv6 mapping the value in this field is used as the frames priority when bits[7:2] of the frames ip tos/diffserv/traffic class value is 0x00 r/w 00 register 145 (0x91): tos priority control register 1 address name description mode default 7 ? 6 dscp[15:14] ipv4 and ipv6 mapping _ for value 0x1c r/w 00 5 ? 4 dscp[13:12] ipv4 and ipv6 mapping _ for value 0x18 r/w 00 3 ? 2 dscp[11:10] ipv4 and ipv6 mapping _ for value 0x14 r/w 00 1 ? 0 dsc p[9:8] ipv4 and ipv6 mapping _ for value 0x10 r/w 00 register 146 (0x92): tos priority control register 2 address name description mode default 7 ? 6 dscp[23:22] ipv4 and ipv6 mapping _ for value 0x2c r/w 00 5 ? 4 dscp[21:20] ipv4 and ipv6 mappin g _ for value 0x28 r/w 00 3 ? 2 dscp[19:18] ipv4 and ipv6 mapping _ for value 0x24 r/w 00 1 ? 0 dscp[17:16] ipv4 and ipv6 mapping _ for value 0x20 r/w 00 register 147 (0x93): tos priority control register 3 address name description mode default 7 ? 6 dscp[31:30] ipv4 and ipv6 mapping _ for value 0x3c r/w 00 5 ? 4 dscp[29:28] ipv4 and ipv6 mapping _ for value 0x38 r/w 00 3 ? 2 dscp[27:26] ipv4 and ipv6 mapping _ for value 0x34 r/w 00 1 ? 0 dscp[25:24] ipv4 and ipv6 mapping _ for value 0x30 r /w 00 april 1, 2014 80 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 148 (0x94): tos priority control register 4 address name description mode default 7 ? 6 dscp[39:38] ipv4 and ipv6 mapping _ for value 0x4c r/w 00 5 ? 4 dscp[37:36] ipv4 and ipv6 mapping _ for value 0x48 r/w 00 3 ? 2 dscp[35:34] ipv4 and ipv6 mapping _ for value 0x44 r/w 00 1 ? 0 dscp[33:32] ipv4 and ipv6 mapping _ for value 0x40 r/w 00 register 149 (0x95): tos priority control register 5 address name description mode default 7 ? 6 dsc p[47:46] ipv4 and ipv6 mapping _ for value 0x5c r/w 00 5 ? 4 dscp[45:44] ipv4 and ipv6 mapping _ for value 0x58 r/w 00 3 ? 2 dscp[43:42] ipv4 and ipv6 mapping _ for value 0x54 r/w 00 1 ? 0 dscp[41:40] ipv4 and ipv6 mapping _ for value 0x50 r/w 00 register 150 (0x96): tos priority control register 6 address name description mode default 7 ? 6 dscp[55:54] ipv4 and ipv6 mapping _ for value 0x6c r/w 00 5 ? 4 dscp[53:52] ipv4 and ipv6 mapping _ for value 0x68 r/w 00 3 ? 2 dscp[51:50] ipv4 and ipv6 mapping _ for value 0x64 r/w 00 1 ? 0 dscp[49:48] ipv4 and ipv6 mapping _ for value 0x60 r/w 00 register 151 (0x97): tos priority control register 7 address name description mode default 7 ? 6 dscp[63:62] ipv4 and ipv6 mapping _ for value 0x7c r/w 00 5 ? 4 dscp[61:60] ipv4 and ipv6 mapping _ for value 0x78 r/w 00 3 ? 2 dscp[59:58] ipv4 and ipv6 mapping _ for value 0x74 r/w 00 1 ? 0 dscp[57:56] ipv4 and ipv6 mapping _ for value 0x70 r/w 00 register 152 (0x98): tos priority control register 8 address name description mode default 7 ? 6 dscp[71:70] ipv4 and ipv6 mapping _ for value 0x8c r/w 00 5 ? 4 dscp[69:68] ipv4 and ipv6 mapping _ for value 0x88 r/w 00 3 ? 2 dscp[67:66] ipv4 and ipv6 mapping _ for value 0x84 r/w 00 1 ? 0 dscp[65:6 4] ipv4 and ipv6 mapping _ for value 0x80 r/w 00 april 1, 2014 81 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 153 (0x99): tos priority control register 9 address name description mode default 7 ? 6 dscp[79:78] ipv4 and ipv6 mapping _ for value 0x9c r/w 00 5 ? 4 dscp[77:76] ipv4 and ipv6 mapping _ for value 0x98 r/w 00 3 ? 2 dscp[75:74] ipv4 and ipv6 mapping _ for value 0x94 r/w 00 1 ? 0 dscp[73:72] ipv4 and ipv6 mapping _ for value 0x90 r/w 00 register 154 (0x9a): tos priority control register 10 addres s name description mode default 7 ? 6 dscp[87:86] ipv4 and ipv6 mapping _ for value 0xac r/w 00 5 ? 4 dscp[85:84] ipv4 and ipv6 mapping _ for value 0xa8 r/w 00 3 ? 2 dscp[83:82] ipv4 and ipv6 mapping _ for value 0xa4 r/w 00 1 ? 0 dscp[81:80] ipv4 and ipv6 mapping _ for value 0xa0 r/w 00 register 155 (0x9b): tos priority control register 11 address name description mode default 7 ? 6 dscp[95:94] ipv4 and ipv6 mapping _ for value 0xbc r/w 00 5 ? 4 dscp[93:92] ipv4 and ipv6 mapping _ for val ue 0xb8 r/w 00 3 ? 2 dscp[91:90] ipv4 and ipv6 mapping _ for value 0xb4 r/w 00 1 ? 0 dscp[89:88] ipv4 and ipv6 mapping _ for value 0xb0 r/w 00 register 156 (0x9c): tos priority control register 12 address name description mode default 7 ? 6 dscp[ 103:102] ipv4 and ipv6 mapping _ for value 0xcc r/w 00 5 ? 4 dscp[101:100] ipv4 and ipv6 mapping _ for value 0xc8 r/w 00 3 ? 2 dscp[99:98] ipv4 and ipv6 mapping _ for value 0xc4 r/w 00 1 ? 0 dscp[97:96] ipv4 and ipv6 mapping _ for value 0xc0 r/w 00 register 157 (0x9d): tos priority control register 13 address name description mode default 7 ? 6 dscp[111:110] ipv4 and ipv6 mapping _ for value 0xdc r/w 00 5 ? 4 dscp[109:108] ipv4 and ipv6 mapping _ for value 0xd8 r/w 00 3 ? 2 dscp[107:106] i pv4 and ipv6 mapping _ for value 0xd4 r/w 00 1 ? 0 dscp[105:104] ipv4 and ipv6 mapping _ for value 0xd0 r/w 00 april 1, 2014 82 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 158 (0x9e): tos priority control register 14 address name description mode default 7 ? 6 dscp[119:118] ipv4 and ipv6 mapping _ for value 0xec r/w 00 5 ? 4 dscp[117:116] ipv4 and ipv6 mapping _ for value 0xe8 r/w 00 3 ? 2 dscp[115:114] ipv4 and ipv6 mapping _ for value 0xe4 r/w 00 1 ? 0 dscp[113:112] ipv4 and ipv6 mapping _ for value 0xe 0 r/w 00 register 159 (0x9f): tos priority control register 15 address name description mode default 7 ? 6 dscp[127:126] ipv4 and ipv6 mapping _ for value 0xfc r/w 00 5 ? 4 dscp[125:124] ipv4 and ipv6 mapping _ for value 0xf8 r/w 00 3 ? 2 dscp[12 3:122] ipv4 and ipv6 mapping _ for value 0xf4 r/w 00 1 ? 0 dscp[121:120] ipv4 and ipv6 mapping _ for value 0xf0 r/w 00 register 176 (0xb0): port 1 control 8 register 192 (0xc0): port 2 control 8 register 208 (0xd0): port 3 control 8 register 224 (0xe0 ): port 4 control 8 register 240 (0xf0): port 5 control 8 address name description mode default 7 ? 4 reserved ro 0000 3 insert source port pvid for untagged packet destination to highest egress port note : enabled by the register 135 bit 2 register 176: insert source port 1 pvid for untagged frame at egress port 5 register 192: insert source port 2 pvid for untagged frame at egress port 5 register 208: insert source port 3 pvid for untagged frame at egress port 5 register 224: insert source port 4 p vid for untagged frame at egress port 5 register 240: insert source port 5 pvid for untagged frame at egress port 4 r/w 0 2 insert source port pvid for untagged packet destination to second highest egress port note : enabled by the register 135 bit 2 reg ister 176: insert source port 1 pvid for untagged frame at egress port 4 register 192: insert source port 2 pvid for untagged frame at egress port 4 register 208: insert source port 3 pvid for untagged frame at egress port 4 register 224: insert source por t 4 pvid for untagged frame at egress port 3 register 240: insert source port 5 pvid for untagged frame at egress port 3 r/w 0 april 1, 2014 83 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 176 (0xb0): port 1 control 8 register 192 (0xc0): port 2 control 8 register 20 8 (0xd0): port 3 control 8 register 224 (0xe0): port 4 control 8 register 240 (0xf0): port 5 control 8 address name description mode default 1 insert source port pvid for untagged packet destination to second lowest egress port note: enabled by the r egister 135 bit 2 register 176: insert source port 1 pvid for untagged frame at egress port 3 register 192: insert source port 2 pvid for untagged frame at egress port 3 register 208: insert source port 3 pvid for untagged frame at egress port 2 register 224: insert source port 4 pvid for untagged frame at egress port 2 register 240: insert source port 5 pvid for untagged frame at egress port 2 r/w 0 0 insert source port pvid for untagged packet destination to lowest egress port note : enabled by the regi ster 135 bit 2 register 176: insert source port 1 pvid for untagged frame at egress port 2 register 192: insert source port 2 pvid for untagged frame at egress port 1 register 208: insert source port 3 pvid for untagged frame at egress port 1 register 224: insert source port 4 pvid for untagged frame at egress port 1 register 240: insert source port 5 pvid for untagged frame at egress port 1 r/w 0 register 177 (0xb1): port 1 control 9 register 193 (0xc1): port 2 control 9 register 209 (0xd1): port 3 contr ol 9 register 225 (0xe1): port 4 control 9 register 241 (0xf1): port 5 control 9 address name description mode default 7 ? 2 reserved ro 0000000 1 4 queue split enable this bit in combination with register16/32/48/64/80 bit 0 will select the split of 1/2/4 queues: {register177 bit 1, register16 bit 0}= 11, reserved. 10 , the port output queue is split into four priority queues or if map 802.1p to priority 0 - 3 mode . 01, the port output queue is split into two priority queues or if map 802.1p to priority 0- 3 mode . 00, single output queue on the port. there is no priority differentiation even though packets are classified into high and low priority r/w 0 0 enable dropping tag 0 = disable tag drop 1 = enable tag drop r/w 0 april 1, 2014 84 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 178 (0xb2): port 1 control 10 register 194 (0xc2): port 2 control 10 register 210 (0xd2): port 3 control 10 register 226 (0xe2): port 4 control 10 register 242 (0xf2): port 5 control 10 address name description mode default 7 enable port transmit queue 3 ratio 0, strict priority, will transmit all the packets from this priority queue 3 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 3 within a certain time r/w 1 6 - 0 port transmit queue 3 ratio[6:0] packet number for transmit queue 3 for highest priority packets in four queues mode r/w 0001000 register 179 (0xb3): port 1 control 11 register 195 (0xc3): port 2 control 11 register 211 (0xd3): port 3 control 11 re gister 227 (0xe3): port 4 control 11 register 243 (0xf3): port 5 control 11 address name description mode default 7 enable port transmit queue 2 ratio 0, strict priority, will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time r/w 1 6 ? 0 port transmit queue 2 ratio[6:0] packet number for transmit queue 2 for high /low priority packets in high /low priority packe ts in four queues mode r/w 0000100 register 180 (0xb4): port 1 control 12 register 196 (0xc4): port 2 control 12 register 212 (0xd4): port 3 control 12 register 228 (0xe4): port 4 control 12 register 244 (0xf4): port 5 control 12 address name descripti on mode default 7 enable port transmit queue 1 rate 0, strict priority, will transmit all the packets from this priority queue 1 before transmit lower priority queue. 1 , bit[6:0] reflect the packet number allow to transmit from this priority queue 1 with in a certain time r/w 1 6 ? 0 port transmit queue 1 ratio[6:0] packet number for transmit queue 1 for low / high priority packets in four queues mode and high priority packets in two queues mode r/w 0000010 april 1, 2014 85 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 181 (0xb5): port 1 control 13 register 197 (0xc5): port 2 control 13 register 213 (0xd5): port 3 control 13 register 229 (0xe5): port 4 control 13 register 245 (0xf5): port 5 control 13 address name description mode default 7 enable port transmit queu e 0 rate 0, strict priority, will transmit all the packets from this priority queue 0 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 0 within a certain time r/w 1 6 ? 0 port transmit queue 0 ratio[6:0] packet number for transmit queue 0 for low est priority packets in four queues mode and low priority packets in two queues mode r/w 0000001 register 182 (0xb6): port 1 rate limit control register 198 (0xc6): port 2 rate limit control re gister 214 (0xd6): port 3 rate limit control register 230 (0xe6): port 4 rate limit control register 246 (0xf6): port 5 rate limit control address name description mode default 7 ? 5 reserved ro 000 4 ingress rate limit flow control enable 1 = flow c ontrol is asserted if the ports receive rate is exceeded 0 = flow control is not asserted if the ports receive rate is exceeded r/w 0 3 ? 2 limit mode ingress limit mode these bits determine what kinds of frames are limited and counted against ingress r ate limiting. = 00, limit and count all frames = 01, limit and count broadcast, multicast, and flooded unicast frames = 10, limit and count broadcast and multicast frames only = 11, limit and count broadcast frames only r/w 00 1 count ifg count ifg by tes = 1, each frames minimum inter frame gap (ifg) bytes (12 per frame) are included in ingress and egress rate limiting calculations. = 0, ifg bytes are not counted. r/w 0 0 co unt pre count preamble bytes = 1, each frames preamble bytes (8 per frame ) are included in ingress and egress rate limiting calculations. = 0, preamble bytes are not counted. r/w 0 april 1, 2014 86 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 183 (0xb7): port 1 priority 0 ingress limit control 1 register 199 (0xc7): port 2 priority 0 ingress limit control 1 register 215 (0xd7): port 3 priority 0 ingress limit control 1 register 231 (0xe7): port 4 priority 0 ingress limit control 1 register 247 (0xf7): port 5 priority 0 ingress limit control 1 address name description mode default 7 res erved ro 0 6 ? 0 port- based priority 0 ingress limit ingress data rate limit for priority 0 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000 000 register 184 (0xb8): port 1 priority 1 ingress limit control 2 register 200 (0xc8): port 2 priority 1 ingress limit control 2 register 216 (0xd8): port 3 priority 1 ingress limit control 2 register 232 (0xe8): port 4 priority 1 ingress limit control 2 register 248 (0xf8): port 5 priority 1 ingress limit control 2 address name description mode default 7 reserved ro 0 6 ? 0 port- based priority 1 ingress limit ingress data rate limit for priority 1 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000 register 185 (0xb9): port 1 priority 2 ingress limit control 3 register 201 (0xc9): port 2 priority 2 ingress limit control 3 register 217 (0xd9): port 3 priority 2 ingress limit control 3 register 233 (0xe9): port 4 priority 2 ingress limit control 3 register 249 (0xf9): port 5 priority 2 ingress limit control 3 address name description mode default 7 reserved ro 0 6 ? 0 port- based pr iority 2 ingress limit ingress data rate limit for priority 2 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000 april 1, 2014 87 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 186 (0xba): port 1 priority 3 ingress limit control 4 register 202 (0xca): port 2 priority 3 ingress limit control 4 register 218 (0xda): port 3 priority 3 ingress limit control 4 register 234 (0xea): port 4 priority 3 ingress limit control 4 register 250 (0xfa): port 5 priority 3 ingress limit control 4 address name description mode default 7 reserved ro 0 6 ? 0 port- based priority 3 ingress limit ingress data rate limit for priority 3 frames ingress traffic from this port is s haped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000 register 187 (0xbb): port 1 queue 0 egress limit control 1 register 203 (0xcb): port 2 queue 0 egress limit control 1 register 219 (0xdb): port 3 queue 0 egress limit control 1 register 235 (0xeb): port 4 queue 0 egress limit control 1 register 251 (0xfb): port 5 queue 0 egress limit control 1 address name description mode default 7 reserved ro 0 6 ? 0 port queue 0 egress limit egress data rate limit for priority 0 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egress limit control registers . in four queues mode, it is lowest priority. in two qu eues mode, it is low priority. r/w 0000000 register 188 (0xbc): port 1 queue 1 egress limit control 2 register 204 (0xcc): port 2 queue 1 egress limit control 2 register 220 (0xdc): port 3 queue 1 egress limit control 2 register 236 (0xec): port 4 queue 1 egress limit control 2 register 252 (0xfc): port 5 queue 1 egress limit control 2 address name description mode default 7 reserved ro 0 6 ? 0 port queue 1 egress limit egress data rate limit for priority 1 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egress limit control registers . in four queues mode, it is low/high priority. in two queues mode, it is high priority. r/w 0000000 april 1, 2014 88 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 189 (0xbd): port 1 queue 2 egress limit control 3 register 205 (0xcd): port 2 queue 2 egress limit control 3 register 221 (0xdd): port 3 queue 2 egress limit control 3 register 237 (0xed): port 4 queue 2 egress limit control 3 register 253 (0xfd): port 5 queue 2 egress limit control 3 address name description mode default 7 reserved ro 0 6 ? 0 port queue 2 egress limit egress data rate limit for priority 2 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egress limit control registers . in four queues mode, it is high/low priority. r/w 0000000 register 190 (0xbe): port 1 queue 3 egress limit control 4 register 206 (0xce): port 2 queue 3 egress limit cont rol 4 register 222 (0xde): port 3 queue 3 egress limit control 4 register 238 (0xee): port 4 queue 3 egress limit control 4 register 254 (0xfe): port 5 queue 3 egress limit control 4 address name description mode default 7 reserved ro 0 6 ? 0 port qu eue 3 egress limit egress data rate limit for priority 3 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egress limit control registers . in four queues mode, it is highest priority. r/w 0000000 note: 1. in t he port priority 0 - 3 ingress rate limit mode, need to set all related ingress/egress ports to two queues or four queues mode . 2. in t he port queue 0 - 3 egress rate limit mode, the highest priority get exact rate limit based on the rate select table, other priori ties packets rate are based on the ratio of the port register control 10/11/12/13 when use more than one egress queue per port. april 1, 2014 89 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub data rate selection table in 100bt table 11 . data rate selection in 100bt rate for 100bt mode 1 mbps <= rate <= 99 mbps rate = 100 mbps less than 1mbps ( see as below ) priority/ queue 0 - 3 ingress/egress limit control register bit[6:0] = decimal rate(decimal integer 1 - 99) 0 or 100 (decimal), 0 is default value decimal 64 k bps 7d101 128 kbps 7d102 192 kbps 7d103 256 kbps 7d104 320 kbps 7d105 384 kbps 7d106 448 kbps 7d107 512 kbps 7d108 576 kbps 7d109 640 kbps 7d110 704 kbps 7d111 768 kbps 7d112 832 kbps 7d113 896 kbps 7d114 960 kbps 7d115 data rate selection table in 10bt table 12 . data rate selection in 10bt rate for 10bt mode 1mbps <= rate <= 9mbps rate = 10 mbps less than 1mbps (see as below) priority/ queue 0 - 3 ingress/egress limit control register bit[6:0]= decimal rate(decimal integer 1 - 9) 0 or 10 (decimal), 0 is default value decimal 64 kbps 7d101 128 kbps 7d102 192 kbps 7d103 256 kbps 7d104 320 kbps 7d105 384 kbps 7d106 448 kbps 7d107 512 kbps 7d108 576 kbps 7d109 640 kbps 7d110 704 kbps 7d 111 768 kbps 7d112 832 kbps 7d113 896 kbps 7d114 960 kbps 7d115 april 1, 2014 90 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub advanced control registers (continued) register 191(0xbf): testing register address name description mode default 7 ? 0 reserved n/a ro 0x80 register 207(0xcf): reserved co ntrol register address name description mode default 7 ? 0 reserved n/a, dont change ro 0x15 register 223(0xdf): test register 2 address name description mode default 7 ? 0 reserved r/w 00000000 register 239(0xef): test register 3 address n ame description mode default 7 reserved n/a, dont change ro 0 6 reserved n/a, dont change ro 0 5 reserved n/a, dont change ro 1 4 ? 0 reserved n/a, dont change ro 0x12 register 255(0xff): testing register 4 address name description mode defau lt 7 ? 0 reserved n/a, don t change ro 0 x00 april 1, 2014 91 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub static mac address table KSZ8895MLub has a static and a dynamic address table. when a da look - up is requested, both tables will be searched to make a packet forwarding decision. when an sa look - up is requested, only the dynamic table is searched for aging, migration, and learning purposes. the static da look - up result will have precedence over the dynamic da look - up result. if there are da matches in both tables, the result from the static table wi ll be used. the static table can only be accessed and controlled by an external spi master (usually a processor). the entries in the static table will not be aged out by KSZ8895MLub . an external device does all addition, modification and deletion. register bit assignments are different for static mac table reads and static mac table write, as shown in table 1 3 and table 1 4. table 13 . format of static mac table for read (32 entries) address name description mode default 63 ? 57 f id filter vlan id, representing one of the 128 active vlans ro 0000 000 56 use fid 1, use (fid+mac) to look - up in static table. 0, use mac only to look - up in static table. ro 0 55 reserved reserved. ro n/a 54 override 1, override spanning tree transmit enable = 0 or receive enable = 0* setting. this bit is used for spanning tree implementation. 0, no override. ro 0 53 valid 1, this entry is valid, the look - up result will be used. 0, this entry is not valid. ro 0 52 ? 48 forwarding ports the 5 bits control the forward ports, example: 00001, forward to port 1 00010, forward to port 2 .. 10000, forward to port 5 00110, forward to port 2 and port 3 11111, broadcasting (excluding the ingress port) ro 00000 47 ? 0 mac address 48 - bit mac address. ro 0x0 examples: 1. static address table read (read the 2nd entry) write to register 110 with 0x10 (read static table selected) write to register 111 with 0x1 (trigger the read operation) then read register 113 (6 3 ? 56) read register 114 (55 ? 48) read re gister 115 (47 ? 40) read register 116 (39 ? 32) read register 117 (31 ? 24) read register 118 (23 ? 16) read register 119 (15 ? 8) read register 120 (7 ? 0) april 1, 2014 92 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub table 14 . format of static mac table for writes (32 entries) address name description mode default 62 ? 56 fid filter vlan id, representing one of the 1 28 active vlans. w 0000 000 55 use fid 1, use (fid+mac) to look - up in static table. 0, use mac only to look - up in static table. w 0 54 override 1, override spanning tree transmit enable = 0 or receive enable = 0 setting. this bit is used for spanning tree implementation. 0, no override. w 0 53 valid 1, this entry is valid, the look - up result will be used. 0, this entry is not valid. w 0 52 ? 48 forward ing ports the 5 bits control the forward ports, example: 00001, forward to port 1 00010, forward to port 2 ..... 10000, forward to port 5 00110, forward to port 2 and port 3 11111, broadcasting (excluding the ingress port) w 00000 47 ? 0 mac address 48 - bit mac address. w 0x0 examples: 1. static address table write (write the 8th entry) write to register 110 with 0x10 (read static table selected) write register 113 (62 ? 56) write register 114 (55 ? 48) write register 115 (47 ? 40) write register 116 (39 ? 32) write register 117 (31 ? 24) write register 118 (23 ? 16) write register 119 (15 ? 8) write register 120 (7 ? 0) write to register 110 with 0x00 (write static table selected) write to register 111 with 0x7 (trigger the write operation) april 1, 2014 93 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub vlan table the vlan table is used for vlan table look - up. if 802.1q vlan mode is enabled (register 5 bit 7 = 1), this table is used to retrieve vlan information that is associated with the ingress packet. there are three fields for fid (filter id), valid , and vlan membership in the vlan table. the three fields must be initialized before the table is used. there is no vid field because 4096 vids are used as a dedicated memory address index into a 1024x52 - bit memory spac e. e ach entry has four vlans . e ach vlan has 13 bits . f our vlans need 52 bits . t here are a total of 1024 entries to support a total of 4096 vlan id s by using dedicated memory address and data bits . r efer to table s below for detail s . fid has 7 - bit s to support 128 active vlans. table 15 . format of static vlan table (support max 4096 vlan id entries and 128 active vla ns) address name description mode initial value suggestion 12 valid 1, the entry is valid. 0, entry is invalid. r/w 0 11 ? 7 membership specify which ports are members of the vlan. if a da look - up fails (no match in both static and dynamic tables), the packet associated with this vlan will be forwarded to ports specified in this field. e.g., 11001 means port 5, port 4 and port 1. r/w 11111 6 ? 0 fid fil ter id. KSZ8895MLub supports 128 active vlans represented by these seven bit fields. fid is the mapped id. if 802.1q vlan is enabled, the look - up in mac table will be based on fid+da and fid+sa. r/w 0 if 802.1q vlan mode is enabled, KSZ8895MLub assigns a vid to every ingress packet when the packet is untagged or tagged with a null vid, the packet is assigned with the default port vid of the ingress port. if the packet is tagged with non - null vid, the vid in the tag is used. the look - up process starts from the vlan table look - up based on vid number with its dedicated memory address and data bits. if the entry is not valid in the vlan table, the packet is dropped and no address learning occurs. if the entry is valid, the fid is retrieved. the fid+da and fi d+sa lookups in mac tables are performed. the fid+da look - up determines the forwarding ports. if fid+da fails for look - up in the mac table , the packet is broadcast to all the members or specified members (excluding the ingress port) based on the vlan table . if fid+sa fails, the fid+sa is learned. t o communicate between different active vlans, set the same fid ; otherwise set a different fid. the vlan table configuration is organized as 1024 vlan sets, each vlan set consists of four vlan entries, to support u p to 4096 vlan entries. each vlan set has 52 bits and should be read or written at the same t ime specified by the indirect address. the vlan entries in the vlan set is mapped to indirect data registers as follow: entry0[12:0] maps to the vlan set bits[12 ? 0] {register119[4:0], register120[7:0]} entry1[12:0] maps to the vlan set bits[25 ? 13]{register117[1:0], register118[7:0], register119[7:5]} entry2[12:0] maps to the vlan set bits[38 ? 26]{register116[6:0], register117[7:2]} entry3[12:0] maps to the vlan set bits[51 ? 39]{register114[3:0], register115[7:0], register116[7]} in order to read one vlan entry, the vlan set is read first and the specific vlan entry information can be extracted. to update any vlan entry, the vlan set is read first then only the desired vlan entry is updated an d the whole vlan set is written back. due to fid in vlan table is 7 - bit, so the vlan table supports unique 128 flow vlan groups. each vlan set address is 10 bits long (maximu m is 1024) in the indirect address register 110 and 111, the bit [9 ? 8] of vlan set address is at bit [1 ? 0] of register 110, a nd the bit [7 ? 0] of vlan set address is at bit [7 - 0] of register 111. each write and read can access to four consecutive vlan entries . april 1, 2014 94 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub examples : 1. vlan table read (r ead the vid=2 entry ) write the indirect control and address registers first write to register 110 (0x6e) with 0x14 (read vlan table selected) write to register 111 (0x6f) with 0x0 (trigger the read operation for vid=0, 1, 2, 3 entries ) then read the indirect data registers bits [38 - 26] for vid=2 entry read register 116 (0x74), (register 116 [6:0] are bits 12 ? 6 of vlan vid=2 entry ) read register 117 (0x75), (register 117 [7:2] are bits 5 ? 0 of vlan vid=2 entry) 2. vlan table write (write the vid= 10 entr y) read the vlan set that contains vid=8, 9, 10, 11 . write to register 110 (0x6e) with 0x14 (read vlan table selected) write to register 111 (0x6f) with 0x02 (trigger the read operation and vid=8, 9, 10, 11 indir ect address) read the vlan set first by the indirect data registers 114, 115, 116, 117, 118, 119, 120 . 3. modify the indirect data registers bits [38 ? 26] by the register 116 bit [6 - 0] and register 117 bit [7 ? 2] as follows: write to register 116 (0x74), (register116 [6:0] a re bits 12 ? 6 of vlan vid= 10 entry ) write to register 117 (0x75), (register117 [7:2] are bits 5 ? 0 of vlan vid= 10 entry) 4. then write the indirect control and address registers write to register 110 (0x6e) with 0x04 (write vlan table selected) write to register 111 (0x6f) with 0x 02 (trigger the write operation and vid= 8, 9, 10, 11 indirect address ) table 16 shows the relationship of the indirect address/data registers and vlan id. table 16 . vlan id and indirect registers indirect address high/low bit [9-0] for vlan sets indirect data registe r s bits for each vlan entry vid numbers vid bit[12 - 2] in vlan tag vid bit[1 - 0] in vlan tag 0 bits[12 ? 0] 0 0 0 0 bits[25 ? 13] 1 0 1 0 bits[38 ? 26] 2 0 2 0 bits[ 51 ? 39] 3 0 3 1 bits[12 ? 0] 4 1 0 1 bits[25 ? 13] 5 1 1 1 bits[38 ? 26] 6 1 2 1 bits[51 ? 39] 7 1 3 2 bits[12 ? 0] 8 2 0 2 bits[25 ? 13] 9 2 1 2 bits[38 ? 26] 10 2 2 2 bits[51 ? 39] 11 2 3 : : : : : : : : : : : : : : : 1023 bits[12 ? 0] 4092 1023 0 1023 bits[25 ? 13] 4093 1023 1 1023 bits[38 ? 26] 4094 1023 2 1023 bits[51 ? 39] 4095 1023 3 april 1, 2014 95 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub dynamic mac address table table 1 7 is read only. the content s are maintained by the KSZ8895MLub only. table 17 . format of dyna mic mac address table (1k entries) address name description mode default 71 mac empty 1, there is no valid entry in the table. 0, there are valid entries in the table. ro 1 70 ? 61 no of valid entries indicates how many valid entries in the table . 0x3ff means 1k entries 0x1 and bit 71 = 0: means 2 entries 0x0 and bit 71 = 0: means 1 entry 0x0 and bit 71 = 1: means 0 entry ro 0 60 ? 59 time stamp 2- bit counters for internal aging ro 58 ? 56 source port the source port where fid+mac is lear ned. 000 port 1 001 port 2 010 port 3 011 port 4 100 port 5 ro 0x0 55 data ready 1, the entry is not ready, retry until this bit is set to 0. 0, the entry is ready. ro 54 ? 48 fid filter id. ro 0x0 47 ? 0 mac address 48 - bit mac address. ro 0x0 april 1, 2014 96 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub dynamic mac address table read/write examples : 1. dynamic mac address table read (read the 1st entry), and retrieve the mac table size: write to register 110 with 0x18 (read dynamic table selected) write to register 111 with 0x0 (trigger the read ope ration) and then read register 112 (71 ? 64) read register 113 (63 ? 56); // the above two registers show # of entries read register 114 (55 ? 48) // if bit 55 is 1, restart (reread) from this register read register 115 (47 ? 40) read register 116 (39 ? 32) read register 117 (31 ? 24) read register 118 (23 ? 16) read register 119 (15 ? 8) read register 120 (7 ? 0) 2. dynamic mac address table read (read the 257th entry), without retrieving # of entries inf ormation: write to register 110 with 0x19 (read dynamic table selected) write to register 111 with 0x1 (trigger the read operation) and then read register 112 (71 ? 64) read register 113 (63 ? 56) read register 114 (55 ? 48) // if bit 55 is 1, restart (reread) from this register read register 115 ( 47 ? 40) read register 116 (39 ? 32) read register 117 (31 ? 24) read register 118 (23 ? 16) read register 119 (15 ? 8) read register 120 (7 ? 0) april 1, 2014 97 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub management information base (mib) counters the management information base (mib) counters are provided on per port basis. these counters are read using indirect memory access as noted in the following tables: port 1 mib counter indirect memory offsets offset counter name description 0x0 rxloprioritybyte rx lo - priority (default) octet count including bad packets. 0x1 rxhiprioritybyte rx hi - priority octet count including bad packets. 0x2 rxundersizepkt rx undersize packets w/good crc. 0x3 rxfragments rx fragment packets w/bad crc, symbol errors or alignment errors. 0x4 rxoversize rx ove rsize packets w/good crc (max: 1536 or 1522 bytes). 0x5 rxjabbers rx packets longer than 1522b w/either crc errors, alignment errors, or symbol errors ( depends on max packet size setting) or rx packets longer than 1916b only. 0x6 rxsymbolerror rx p ackets w/ invalid data symbol and legal preamble, packet size. 0x7 rxcrcerror rx packets within (64,1522) bytes w/an integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x8 rxalignmenterror rx packets within (64,1522) bytes w/a non - integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x9 rxcontrol8808pkts the number of mac control frames received by a port with 88 - 08h in ethertype field. 0xa rxpausepkts the number of pause frames received by a port. pause frame is qualified with ethertype ( 88 - 08h), da, control opcode (00 ? 01), data length (64b min), and a valid crc. 0xb rxbroadcast rx good broadcast packets (not including errored broadcast packets or valid multicast packets). 0xc rxmulticast rx good multicast packets (not including mac control frames, errored multicast pack ets or valid broadcast packets). 0xd rxunicast rx good unicast packets. 0xe rx64octets total rx packets (bad packets included) that we re 64 octets in length. 0xf rx65to127octets total rx packets (bad packets included) that are between 65 and 127 octets in length. 0x10 rx128to255octets total rx packets (bad packets included) that are between 128 and 255 octets in length. 0x11 r x256to511octets total rx packets (bad packets included) that are between 256 and 511 octets in length. 0x12 rx512to1023octets total rx packets (bad packets included) that are between 512 and 1023 octets in length. 0x13 rx1024to1522octets total rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting). 0x14 txloprioritybyte tx lo - priority good octet count, including pause packets. 0x15 txhiprioritybyte tx hi - priority good octet count, including pause packets. 0x16 txlatecollision the number of times a collision is detected later than 512 bit - times into the tx of a packet. 0x17 txpausepkts the number of pause frames transmitted by a port. 0x18 txbroadcastpkts tx good broadcast packets (not including errored broadcast or valid multicast packet s). april 1, 2014 98 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub port 1 mib counter indirect memory offsets (continued) offset counter name description 0x19 txmulticastpkts tx good multicast packets (not including errored multicast packets or valid broadcas t packets). 0x1a txunicastpkts tx good unicast packets. 0x1b txdeferred tx packets by a port for which the 1st tx attempt is delayed due to the busy medium. 0x1c txtotalcollision tx total collision, half - duple x only. 0x1d txexcessivecollision a count of frames for which tx fails due to excessive collisions. 0x1e txsinglecollision successfully tx frames on a port for which tx is inhibited by exactly one collision. 0x1f txmultiplecollision successfull y tx frames on a port for which tx is inhibited by more than one collision. format of per port mib counter for port 2, the base is 0x20, same offset definition (0x20 - 0x3f) for port 3, the base is 0x40, same offset definition (0x40 - 0x5f) for port 4, the base is 0x60, same offset definition (0x60 - 0x7f) for port 5, the base is 0x80, same offset definition (0x80 - 0x9f) address name description mode default format of per port mib counters (16 entries) 31 overflow 1, counter overflow. 0, no counter o verflow. ro 0 30 count valid 1, counter value is valid. 0, counter value is not valid. ro 0 29 ? 0 counter values counter value. ro 0 table 18 . all port dropped packet mib counters offset counter name description 0x100 port1 tx drop packets tx packets dropped due to lack of resources. 0x101 port2 tx drop packets tx packets dropped due to lack of resources. 0x102 port3 tx drop packets tx packets dropped due to lack of resources. 0x103 port4 tx drop packets tx packets dropped due to lack of resources. 0x104 port5 tx drop packets tx packets dropped due to lack of resources. 0x105 port1 rx drop packets rx packets dropped due to lack of resources. 0x106 port2 rx drop packets rx packets dropped due to lack of resources. 0x107 port3 rx drop packets rx packets dropped due to lack of resources. 0x108 port4 rx drop packets rx packets dropped due to lack of resources. 0x109 port5 rx drop packets rx packets dropped due to lack of resources. april 1, 2014 99 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub table 19 . format of all dropped packet mib counters address name description mode default 30 ? 16 reserved reserved. n/a n/a 15 ? 0 counter values counter value. ro 0 note that all port dropped packet mib counters do not indicate overflow or validity; therefore the application must keep track of overflow and valid conditions. the KSZ8895MLub provides total 34 mib counter per port. these counter are used to monitor the por t detail activity for network management and maintenance. these mib counters are read using indirect memory ac cess as as noted in the following examples: programming examples: 1. mib counter read (read port 1 r x64 octets counter) write to register 110 with 0x1c (read mib counters selected) write to register 111 with 0xe (trigger the read operation) then read register 117 (counter value 31 ? 24) // if bit 31 = 1, there was a counter overflow // if bit 30 = 0, restart (reread) from this register read register 118 (counter value 23 ? 16) read register 119 (counter value 15 ? 8) read register 120 (counter value 7 ? 0) 2. mib counter read (read port 2 rx64octets counter) write to register 110 with 0x1c (read mib counter selected) write to register 111 with 0x2e (trigger the read operation) then read registe r 117 (counter value 31 ? 24) //if bit 31 = 1, there was a counter overflow //if bit 30 = 0, restart (reread) from this register read register 118 (counter value 23 ? 16) read register 119 (counter value 15 ? 8) read register 120 (counter value 7 ? 0) 3. mib counter read (read port 1 tx drop packets) write to register 110 with 0x1d write to register 111 with 0x00 then read register 119 (counter value 15 ? 8) read register 120 (counter value 7 ? 0) april 1, 2014 100 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub note that to read out all the counters, the best performance over the spi bus is (160+3) 8 80 = 104us, where there are 160 registers, 3 overhead, 8 clocks per access, at 12.5mhz. in the heaviest condition, the by te counter will overflow in 2 minutes. it is recommended that the software read all the counters at least every 30 seconds. the per port mib counters are designed as read clear. a per port mib counter will be cleared after it is accessed. al l port dropped packet mib counters are not cleared after they are accessed. the application needs to keep track of overflow and valid conditions on these counters. april 1, 2014 101 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub miim registers all the registers defined in this section can be also accessed via the spi interface. note that different mapping mechanisms are used for miim and spi. the phyad defined in ieee is assigned as 0x1 for port 1, 0x2 for port 2, 0x3 for port 3 and 0x4 for port 4 . the regad supported are 0 x0 - 0x5 (0h - 5h), 0x1d (1dh) and 0x1f (1fh) . register 0h: mii control address name description mode default 15 soft reset 1, phy soft reset . 0, normal operation. r/w (sc) 0 14 loop back 1 = perform mac loopback, loop back path as follows: assume the loop - back is at port 1 mac, port 2 is the monitor port. port 1 mac loopback (port 1 reg. 0, bit 14 = 1) start: rxp2/r xm2 (port 2). can also start from port 3, 4, 5 loopback: mac/phy interface of port 1s mac end: txp2/txm2 (port 2). can also end at port 3, 4, 5 respectively setting address ox3,4,5 reg. 0, bit 14 = 1 will perform mac loopback on port 3, 4, 5 respectively. 0 = normal operation. r/w 0 13 force 100 1, 100mbps. 0, 10mbps. r/w 1 12 an enable 1, auto - negotiation enabled. 0, auto - negotiation disabled. r/w 1 11 power down 1, power down. 0, normal operation. r/w 0 10 phy isolate 1, electrical phy isolation of phy from tx+/tx -. 0, normal operation. r/w 0 9 restart an 1, restart auto - negotiation. 0, normal operation. r/w 0 8 force full duplex 1, full duplex. 0, half duplex. r/w 0 7 collision test not supported. ro 0 6 reserved ro 0 5 hp_mdix 1 = hp auto mdi/mdi - x mode 0 = micrel auto mdi/mdi - x mode r/w 1 4 force mdi 1, force mdi. 0, normal operation. r/w 0 3 disable auto mdi/mdi - x 1, disable auto mdi/mdi - x. 0, normal operation. r/w 0 2 disable f ar end fault 1, disable far end fault detection. 0, normal operation. r/w 0 1 disable transmit 1, disable transmit. 0, normal operation. r/w 0 0 disable led 1, disable led. 0, normal operation. r/w 0 april 1, 2014 102 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub miim registers (continued) register 1h: mii status address name description mode default 15 t4 capable 0, not 100 baset4 capable. ro 0 14 100 full capable 1, 100base - tx full - duplex capable. 0, not capable of 100base - tx full - duplex. ro 1 13 100 half capable 1, 100base - tx half - dupl ex capable. 0, not 100base - tx half - duplex capable. ro 1 12 10 full capable 1, 10base - t full - duplex capable. 0, not 10base - t full - duplex capable. ro 1 11 10 half capable 1, 10base - t half - duplex capable. 0, 10base - t half - duplex capable. ro 1 10 ? 7 reserved ro 0 6 preamble suppressed not supported. ro 0 5 an complete 1, auto - negotiation complete. 0, auto - negotiation not completed. ro 0 4 far end fault 1, far end fault detected. 0, no far end fault detected. ro 0 3 an capable 1 , auto - negotiation capable. 0, not auto - negotiation capable. ro 1 2 link status 1, link is up. 0, link is down. ro 0 1 jabber test not supported. ro 0 0 extended capable 0, not extended register capable. ro 0 register 2h: phyid hi gh address name description mode default 15 ? 0 phyid high high order phyid bits. ro 0x0022 register 3h: phyid low address name description mode default 15 ? 0 phyid low low order phyid bits. ro 0x1450 april 1, 2014 103 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub miim registers (continued) r egister 4h: advertisement ability address name description mode default 15 next page not supported. ro 0 14 reserved ro 0 13 remote fault not supported. ro 0 12 ? 11 reserved ro 0 10 pause 1, advertise pause ability. 0, do not advert ise pause ability. r/w 1 9 reserved r/w 0 8 adv 100 full 1, advertise 100 full - duplex ability. 0, do not advertise 100 full - duplex ability. r/w 1 7 adv 100 half 1, advertise 100 half - duplex ability. 0, do not advertise 100 half - duplex ability . r/w 1 6 adv 10 full 1, advertise 10 full - duplex ability. 0, do not advertise 10 full - duplex ability. r/w 1 5 adv 10 half 1, advertise 10 half - duplex ability. 0, do not advertise 10 half - duplex ability. r/w 1 4 ? 0 selector field 802.3 ro 0 0001 register 5h: link partner ability address name description mode default 15 next page not supported. ro 0 14 lp ack not supported. ro 0 13 remote fault not supported. ro 0 12 ? 11 reserved ro 0 10 pause link partner pause capability. ro 0 9 reserved ro 0 8 adv 100 full link partner 100 full capability. ro 0 7 adv 100 half link partner 100 half capability. ro 0 6 adv 10 full link partner 10 full capability. ro 0 5 adv 10 half link partner 10 half ca pability. ro 0 4- 0 reserved ro 00001 april 1, 2014 104 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub miim registers (continued) register 1dh: linkmd control/st atu s address name description mode default 15 vct_enable 1 = enable cable diagnostic. aftervct test has completed, this bit will be self - cleared. 0 = indicate cable diagnostic test (if enabled) has completed and the status information is valid for read. r/w (sc) 0 14 - 13 vct_result 00 = normal condition 01 = open condition detected in cable 10 = short condition detected in cable 11 = cable diagnostic test has failed ro 00 12 vct 10m short 1 = less than 10 meter short ro 0 11 -9 reserved ro 0 8-0 vct_fault_count distance to the fault. its approximately 0.4m*vct_fault_count [8:0] ro 000000000 register 1fh: phy special control/status ad dress name description mode default 15 ? 11 reserved ro 0000000000 10 ? 8 port operation mode indication indicate the current state of port operation mode: [000] = reserved [001] = still in auto - negotiation [010] = 10base- t half duplex [011] = 100ba se- tx half duplex [100] = reserved [101] = 10base- t full duplex [110] = 100base- tx full duplex [111] = phy/mii isolate ro 000 7 ? 6 reserved n/a, dont change r/w xx 5 polrvs 1 = polarity is reversed 0 = polarity is not reversed ro 0 4 mdi - x status 1 = mdi 0 = mdi -x ro 0 3 force_lnk 1 = force link pass 0 = normal operation r/w 0 2 pwrsave 1 = enable power save 0 = disable power save r/w 0 april 1, 2014 105 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub register 1fh: phy special control/status (continued) 1 remote loopback 1 = perform remote loopback, loop back pa th as follows: port 1 (phy id address 0x1 reg. 1f, bit 1 = 1) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 1s phy end: txp1/txm1 (port 1) setting phy id address 0x2,3,4,5 reg. 1fh, bit 1 = 1 wil l perform remote loopback on port 2, 3, 4, 5. 0 = normal operation. r/w 0 0 reserved ro 0 april 1, 2014 106 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub absolute maximum ratings (1) supply voltage (v ddar , v ddap , v ddc ) ......................... C 0.5v to +2.4v (v ddat , v ddio ) ................................... C 0.5v to +4.0v input voltage .......................................... C 0.5v to +4.0v output voltage ....................................... C 0. 5v to +4.0v lead temperature (soldering, 10 sec.) ............... 26 0c storage temperature (t s ) .................. C 55c to +150c h bm esd rating .................................................... 5 kv operating ratings (2) supply voltage (v ddar , v ddap , v ddc ) ........................ +1.1 4 v to +1.2 6v (v ddat ) ............................... .. +3.1 3 5v to +3.4 6 5v (v ddio @ 3.3v ) ................................ . + 3.1 35v to + 3. 46 5v (v ddio @ 2.5v) ................................ . +2. 37 5v to + 2. 62 5v (v ddio @ 1.8v) ................................ . +1. 710 v to + 1. 890 v ambient temperature (t a ) industrial/automotive ............................... C 40c to +85c package thermal resistance (3) lqfp ( ja ) no air flow ............................. 48. 22 c/w lqfp ( jc ) no air flow .............................. 13. 95 c/w electrical characteristics (4 , 5 ) v in = 1.2v/3.3v (typ.); t a = 25c . symbol parameter condition min. typ. max. units 100base - tx operation all ports 100% utilization i dx 100base- tx (transmitter) 3.3v analog v ddat 86 ma i dd a 100base- tx 1.2v analog v ddar 22 ma i dd c 100base- tx 1.2v digital v ddc 42 ma i ddio 100base- tx (digital io) standalone switch v ddio 2 ma i ddio 3.3v digital io port 5 sw5 - mii mac/phy v ddio 22/38 ma 10base - t operation all ports 100% utilization i dx 10base- t (transmitter) 3.3v analog v ddat 107 ma i dd a 10base- t 1.2v analog v dd ar 8.6 ma i dd c 10base- t 1.2v digital v ddc 44 ma i ddio 10base- tx (digital io) standalone switch v dd io 2 ma i ddio 3.3v digital io port 5 sw5 - mii mac/phy v ddio 5/18 ma auto - negotiation mode i dx 10base- t (transmitter) 3.3v analog v ddat 55 ma i dd a 10base- t 1.2v analog v dd ar 22 ma i edm 10base- t 1.2v digital v ddc 46 ma i ddio 10b ase- t (digital io) standalone switch v ddio 1.5 ma notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. unused inputs must always be tied to an appropriate logic voltage level (ground or v dd ). 3. no heat spreader in package. the thermal junction to ambient ( ja ) and the thermal junction to case ( jc ) are under air velocity 0m/s. 4. specification for packaged product only. there is no an additional transformer consumption du e to use on chip termination technology with internal biasing for 10bese - t and 100base - tx. 5. measurements were taken with operating ratings. april 1, 2014 107 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub electrical characteristics (4, 5) (continued) v in = 1.2v/3.3v (typ.); t a = 25c symbol parameter condition min. typ . max. units power management mode (standalone) i psm1 power - saving mode 3.3v v ddat + v dd io 35 ma i psm2 power - saving mode 1.2v v dd ar + vddc 55 ma i spdm1 soft power - down mode 3.3v v ddat + v dd io 2 ma i spdm2 soft power - down mode 1.2v v dd ar + vddc 1.8 ma i edm1 energy - detect mode + pll off 3.3v v ddat + v dd io 5.5 ma i edm2 energy -d etect mode + pll off 1.2v v dd ar + vddc 1.5 ma cmos inputs v ih input high voltage (vddio=3.3/2.5/1.8v) 2.0/1.8 /1.3 v v il input low voltage (vd dio=3.3/2.5/1.8v) 0.8/0.7 /0. 5 v i in input current (excluding pull - up /pull- down ) v in = gnd ~ v ddio C 10 10 a cmos outputs v oh output high voltage (vddio=3.3/2.5/1.8v) i oh = C 8ma 2.4/ 2.0 /1.5 v v ol output low voltage (vddio=3.3/2.5/1.8v) i ol = 8ma 0.4/0.4 /0. 3 v i oz output tri - state leakage v in = gnd ~ v ddio 10 a 100base - tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100? termination on the differential output 0.95 1.05 v v imb ou tput voltage imbalance 100? termination on the differential output 2 % t r t t rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.5 ns overshoot 5 % output jitters peak - to - peak 0 0.75 1.4 ns 10base - t receive v sq squelch threshold 5mhz square wave 300 400 585 mv 10base - t transmit (measured differentially after 1:1 transformer) v ddat = 3.3v v p peak differential output voltage 100? termination on the differential output 2.2 2. 5 2.8 v output jitte rs peak - to - peak 1.4 3.5 ns rise/fall times 28 30 ns april 1, 2014 108 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub timing diagrams eeprom timing figure 13 . eeprom interface input receive timing diagram figure 14 . eeprom interface output tr ansmit timing diagram table 20 . eeprom timing parameters symbol parameter min. typ. max. units t cyc1 clock cycle 16384 ns t s1 set- up time 20 ns t h1 hold time 20 ns t ov1 output valid 4096 4112 4128 ns april 1, 2014 109 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub timing diagrams (continued) sni timing figure 15 . sni input timing figure 16 . sni output timing table 21 . sni timing parameters symbol parameter min. typ. max. units t cyc2 clock cycle 100 ns t s2 set- up time 10 ns t h2 hold time 0 ns t o2 output valid 0 3 6 ns april 1, 2014 110 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub timing diagrams (continued) mii timing figure 17 . mac mode mii timing C data received from mii figure 18 . mac mode mii timing C data transmitted from mii table 22 . mac mode mii timing parameters symbol parameter 10base - t/100base - tx min. typ. max. units t cyc3 clock cycle 400/40 ns t s3 set- up time 10 ns t h3 hold time 5 ns t ov3 output valid 3 9 25 ns april 1, 2014 111 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub timing diagrams (continued) mii timing (continued) figure 19 . phy mode mii timing C data received from mii figure 20 . phy mode mii timing C data transmitted from mii table 23 . phy mode mii timing parameters symbol parameter 10baset/100baset min. typ. max. units t cyc4 clock cycle 400/40 ns t s4 set- up time 10 ns t h4 hold time 0 ns t ov4 output valid 16 20 25 ns april 1, 2014 112 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub timing diagrams (continued) spi timing figure 21 . spi input timing table 24 . spi input timing parameters symbol parameter min. typ. max. units f c clock frequency 25 mhz t chsl spis_ n inactive hold time 10 ns t slch spis_n active set - up time 10 ns t chsh spis_n active hold time 10 ns t shch spis_n inactive set - up time 10 ns t shsl spis_n deselect time 20 ns t dvch data input set - up time 5 ns t chdx data input hold t ime 5 ns t clch clock rise time 1 s t chcl clock fall time 1 s t dldh data input rise time 1 s t dhdl data input fall time 1 s april 1, 2014 113 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub timing diagrams (continued) spi timing (continued) figure 22 . spi output timing table 25 . spi output timing parameters symbol parameter min. typ. max. units f c clock frequency 25 mhz t clqx spiq hold time 0 0 ns t clqv clock low to spiq valid 15 ns t ch clock high time 18 ns t cl c lock low time 18 ns t qlqh spiq rise time 50 ns t qhql spiq fall time 50 ns t shqz spiq disable time 15 ns april 1, 2014 114 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub timing diagrams (continued) auto - negotiation timing figure 23 . auto - negotiation timing table 26 . auto - negotiation timing parameters symbols parameters min. typ. max. units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per burst 17 33 april 1, 2014 115 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub timing diagrams (continued) reset timing figure 24 . reset timing table 27 . reset timing parameters sym bol parameter min. typ. max. units t sr stable supply voltages to reset high 10 ms t cs configuration set - up time 50 ns t ch configuration hold time 50 ns t rc reset to strap - in pin output 50 ns tvr 3.3v rise time 100 s april 1, 2014 116 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub reset circuit diagram micrel recommends the following discrete reset circuit as shown in figure 25 when powering up the ks8895 mlub b device. for the application where the reset circuit signal comes from another device (e. g., cpu, fpga, etc), we recommend the reset circuit as shown in figure 2 6. figure 25 . recommended reset circuit figure 26 . recommended circuit for interfacing with cpu/fpga reset at power - on - reset, r, c, and d1 provide the necessary ramp rise time to reset the micrel device. the reset out rst_out_n from cpu/fpga provides the warm reset after power - up. april 1, 2014 117 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub isolation transformer selection one simple 1:1 isolation transformer is needed at the line interface. an isolation transformer wi th integrated common - mode choke is recommended for exceeding fcc requirements at line side . request to separate the center taps of rx/tx at chip side. table 28 gives recommended transformer characteristics. table 28 . transformer selection crite ria characteristics name value test condition turns ratio 1 ct : 1 ct open - circuit inductance (min.) 350h 100mv, 100khz, 8ma insertion loss (max.) 1. 1db 0 .1 mhz to 100 mhz hipot (min.) 1500vrms note: 1. the ieee 802.3u standard for 100base - tx assumes a transformer loss of 0.5db. for the transmit line transformer, insert ion loss of up to 1.3db can be compensated by increasing the line drive current by means of reducing the iset resistor v alue. 2. the center taps of rx and tx should be isolated for the low power consumption. table 29 provide transformer vendors provide compatible magnetic parts for micrels device. table 29 . qualified magnetic vendors vendor s and part s auto mdix # of ports vendor s and part s auto mdix # of ports pulse h1 6 64 nl yes 4 pulse h1102 yes 1 pulse h1164nl yes 4 bel fuse s558 - 5999 - u7 yes 1 tdk tla - 6t718 a yes 1 ycl pt163020 yes 1 lankom lf - h41s yes 1 transpower hb726 yes 1 datatronic nt79075 yes 1 delta lf8505 yes 1 reference crystal selection table 30 . typical reference crystal characteristics chara cteristics value units frequency 25.00000 mhz frequency tolerance (max .) < = 50 ppm load capacitance (max.) 18 ? 27 pf series resistance 40 ? april 1, 2014 118 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub package information 128 - pin lqfp package april 1, 2014 119 revision 2. 1 downloaded from: http:///
micrel, inc. KSZ8895MLub micrel, inc. 2180 fortune drive san jose, ca 95131 usa te l +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or comp leteness of the information furnished in th is data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its us e. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrels terms and conditions of sale for such products, mic rel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/ or use of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any paten t, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appl iances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are device s or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to res ult in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devic es or systems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 20 11 micrel, incorporated. april 1, 2014 120 revision 2. 1 downloaded from: http:///

▲Up To Search▲

Price & Availability of KSZ8895ML

	To Download KSZ8895ML Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .